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Along with the increasing integration density and decreased feature size of current semiconductor technology, heterointegration of the Si‐based devices with diamond has acted as a promising strategy to relieve the existing heat dissipation problem. As one of the heterointegration methods, the microwave plasma chemical vapor deposition (MPCVD) method is utilized to synthesize large‐scale diamond films on a Si substrate, while distinct structures appear at the Si‐diamond interface. Investigation of the formation mechanisms and modulation strategies of the interface is crucial to optimize the heat dissipation behaviors. By taking advantage of electron microscopy, the formation of the epitaxial β‐SiC interlayer is found to be caused by the interaction between the anisotropically sputtered Si and the deposited amorphous carbon. Compared with the randomly oriented β‐SiC interlayer, larger diamond grain sizes can be obtained on the epitaxial β‐SiC interlayer under the same synthesis condition. Moreover, due to the competitive interfacial reactions, the epitaxial β‐SiC interlayer thickness can be reduced by increasing the CH4/H2 ratio (from 3% to 10%), while further increase in the ratio (to 20%) can lead to the broken of the epitaxial relationship. The above findings are expected to provide interfacial design strategies for multiple large‐scale diamond applications. [ABSTRACT FROM AUTHOR]

Abstract Along with the increasing integration density and decreased feature size of current semiconductor technology, heterointegration of the Si‐based devices with diamond has acted as a promising strategy to relieve the existing heat dissipation problem. As one of the heterointegration methods, the microwave plasma chemical vapor deposition (MPCVD) method is utilized to synthesize large‐scale diamond films on a Si substrate, while distinct structures appear at the Si‐diamond interface. Investigation of the formation mechanisms and modulation strategies of the interface is crucial to optimize the heat dissipation behaviors. By taking advantage of electron microscopy, the formation of the epitaxial β‐SiC interlayer is found to be caused by the interaction between the anisotropically sputtered Si and the deposited amorphous carbon. Compared with the randomly oriented β‐SiC interlayer, larger diamond grain sizes can be obtained on the epitaxial β‐SiC interlayer under the same synthesis condition. Moreover, due to the competitive interfacial reactions, the epitaxial β‐SiC interlayer thickness can be reduced by increasing the CH4/H2 ratio (from 3% to 10%), while further increase in the ratio (to 20%) can lead to the broken of the epitaxial relationship. The above findings are expected to provide interfacial design strategies for multiple large‐scale diamond applications.

[Display omitted] • Vertically aligned CdS nanorod arrays were integrated on the graphite. • Model system exhibited superior photocatalytic reactions and photostability. • Hetero-integration of CdS on graphite enhanced photoelectrochemical performance. One-dimensional (1D) cadmium sulfide (CdS) nanostructures in photosynthetic systems have attracted attention because of their effective transport pathways for charge extraction which are essential for efficient photocatalytic and photoelectrochemical systems. Despite the numerous benefits of aligned 1D CdS nanostructures in photosynthetic systems, limited attention has been paid to hetero - integrating 1D CdS arrays on substrates with rapid charge extraction capabilities and practical applicability. Herein, we report the fabrication of vertically aligned CdS nanorod arrays on graphite substrates, in which electron transport pathways are rationally designed for effective photocatalysts and photoanodes. Specifically, CdS nanorod arrays integrated on graphite substrates exhibited photocatalytic reactions with excellent reusability and photostability owing to their superior bifacial properties compared to the control free-standing nanostructures. The proposed system also demonstrated excellent photoelectrochemical performance relative to control CdS nanorod arrays integrated on fluorine-doped tin oxide substrates because of the enhanced separation and extraction of photogenerated electrons combined with curvilinear surfaces. [ABSTRACT FROM AUTHOR]

A high figure‐of‐merit UV‐C solar‐blind photodetector (PD) fabricated from thin‐film beta‐gallium oxide (β‐Ga2O3) grown on n‐Si substrates by plasma‐assisted molecular beam epitaxy is demonstrated. Film growth sequences for nucleation of Ga2O3 on (100)‐ and (111)‐oriented Si substrates are developed, and the influence of crucial growth parameters is systematically investigated, namely, substrate temperature, oxygen flow rate, and plasma power on the functional properties of the PDs. The PDs show an ultra‐high responsivity of 837 A W−1 and a fast ON/OFF time below 4 ms at −5 V. In addition, they display strong rectifying properties and a sharp cutoff below 280 nm with the average responsivities between 10 and 80 A W−1, a detectivity on the order of 1010 Jones, and rise/fall times between 4 and 500 ms. High photoconductive gain is likely to be due to the mid‐bandgap donor/acceptor defect levels, including oxygen vacancies in the form of self‐trapped holes. It is demonstrated that these defect levels can be modified by controlling the growth conditions, thereby allowing for tailoring of the PD characteristics for specific applications. The methodology represents a cost‐effective solution over homoepitaxial approaches, with characteristics that meet or exceed those reported previously, offering new possibilities for on‐wafer integration with Si opto‐electronics.

The heterointegration of graphene with semiconductor materials and the development of graphene-based hybrid functional devices are heavily bound to the control of surface energy. Although remote epitaxy offers one of the most appealing techniques for implementing 3D/2D heterostructures, it is only suitable for polar materials and is hugely dependent on the graphene interface quality. Here, the growth of defect-free single-crystalline germanium (Ge) layers on a graphene-coated Ge substrate is demonstrated by introducing a new approach named anchor point nucleation (APN). This powerful approach based on graphene surface engineering enables the growth of semiconductors on any type of substrate covered by graphene. Through plasma treatment, defects such as dangling bonds and nanoholes, which act as preferential nucleation sites, are introduced in the graphene layer. These experimental data unravel the nature of those defects, their role in nucleation, and the mechanisms governing this technique. Additionally, high-resolution transmission microscopy combined with geometrical phase analysis established that the as-grown layers are perfectly single-crystalline, stress-free, and oriented by the substrate underneath the engineered graphene layer. These findings provide new insights into graphene engineering by plasma and open up a universal pathway for the heterointegration of high-quality 3D semiconductors on graphene for disruptive hybrid devices., (© 2023 The Authors. Small published by Wiley‐VCH GmbH.)

We present a wafer-level heterointegrated indium phosphide double heterobipolar transistor on silicon germanium bipolar-complementary metal oxide semiconductor (InP DHBT on SiGe BiCMOS) process which relies on adhesive wafer bonding. Subcircuits are co-designed in both technologies, SiGe BiCMOS and InP DHBT, with more than 300 GHz bandwidth microstrip interconnects. The 250 nm SiGe HBTs offer cutoff frequencies around 200 GHz, the 800 nm InP DHBTs exceed 350 GHz. Heterointegrated signal sources are demonstrated including a 328 GHz quadrupling source with [ABSTRACT FROM AUTHOR]

Abstract: Recently Philips launched their first highly integrated cellular RF-transceiver systems using a new Si-based System-in-Package (SiP) technology. This technology utilizes back-end processing to integrate passive components onto a Si-substrate that serves as a platform for heterogeneous integration with active dies, MEMS dies, etc. As an example, a transceiver IC is flip-chip mounted onto this passive component substrate, thus minimizing interconnect parasitics and footprint area. Next, this sub-assembly is flipped back into a standard single IC-sized lead frame package. This paper reports on such Si-based SiP transceiver modules and the underlying technologies. Here, the passive die is made by the so-called PICS (Passive Integration Connecting Substrate) technology that integrates passive components on one die, such as high-Q inductors, resistors, accurate MIM capacitors and, in particular, high-density (∼20–30 nF/mm2) MOS ‘trench’ capacitors for decoupling. These MOS capacitors integrated in RF power amplifiers showed superior signal stability compared to discrete ceramic capacitors. Ultralow-loss factors were measured: series inductance ESL <40 pH and resistance ESR <150 mΩ, combined with superior dielectric breakdown voltage (30 V), low leakage (<1 nA/mm2 at 22 V) and long lifetime of 10 years at 100 °C and 10 V). [Copyright &y& Elsevier]

[Display omitted] • GaN tetrapodal structures are successfully integrated on the 3D faceted Si surfaces. • 3D tetrapodal GaN-on-Si structures show the improved material quality of GaN. • 3D GaN-on-Si LEDs enhance the light extraction efficiencies by ~ 300%. • 3D GaN-on-Si LEDs exhibit multi-color light emission with tunable colors. Gallium nitride (GaN) light-emitting diodes (LEDs) on silicon (Si) substrates have been highlighted due to the potentials to achieve significant cost reduction, effective thermal management, and highly directional light emission, by replacing the conventional sapphire substrates with the opportunities to adopt the well-established Si-based semiconducting technologies. However, large mismatch of physical properties between Si and GaN considerably lowers the material quality of GaN and the corresponding device performances. Herein, we employ three-dimensional faceted Si surfaces (3D faceted Si) to effectively release the generated strain energy during the hetero-epitaxial growth of GaN on Si for fabricating high performance GaN-on-Si LEDs. The resulting outcome not only includes the unique morphology of 3D tetrapodal GaN layers on 3D faceted Si to form space-filling arrays for efficient device utilization, but also contains the excellent material quality of the hetero-integrated GaN layers, comparable to that grown on planar sapphire substrates. Consequently, those 3D tetrapodal GaN-on-Si LEDs exhibit the excellent light extraction characteristics due to their shapes to effectively suppress total internal reflection of generated light. In addition, the anisotropic formation of active layers in the 3D tetrapodal GaN-on-Si LEDs performs multi-color emission characteristics with tunable color capabilities. [ABSTRACT FROM AUTHOR]

Remote epitaxy has drawn attention as it offers epitaxy of functional materials that can be released from the substrates with atomic precision, thus enabling production and heterointegration of flexible, transferrable, and stackable freestanding single-crystalline membranes. In addition, the remote interaction of atoms and adatoms through two-dimensional (2D) materials in remote epitaxy allows investigation and utilization of electrical/chemical/physical coupling of bulk (3D) materials via 2D materials (3D-2D-3D coupling). Here, we unveil the respective roles and impacts of the substrate material, graphene, substrate-graphene interface, and epitaxial material for electrostatic coupling of these materials, which governs cohesive ordering and can lead to single-crystal epitaxy in the overlying film. We show that simply coating a graphene layer on wafers does not guarantee successful implementation of remote epitaxy, since atomically precise control of the graphene-coated interface is required, and provides key considerations for maximizing the remote electrostatic interaction between the substrate and adatoms. This was enabled by exploring various material systems and processing conditions, and we demonstrate that the rules of remote epitaxy vary significantly depending on the ionicity of material systems as well as the graphene-substrate interface and the epitaxy environment. The general rule of thumb discovered here enables expanding 3D material libraries that can be stacked in freestanding form.

An important pathway for cost-effective light energy conversion devices, such as solar cells and light emitting diodes, is to integrate III-V (e.g., GaN) materials on Si substrates. Such integration first necessitates growth of high crystalline III-V materials on Si, which has been the focus of many studies. However, the integration also requires that the final III-V/Si structure has a high light energy conversion efficiency. To accomplish these twin goals, we use single-crystalline microsized Si pillars as a seed layer to first grow faceted Si structures, which are then used for the heteroepitaxial growth of faceted GaN films. These faceted GaN films on Si have high crystallinity, and their threading dislocation density is similar to that of GaN grown on sapphire. In addition, the final faceted GaN/Si structure has great light absorption and extraction characteristics, leading to improved performance for GaN-on-Si light energy conversion devices.