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FPGA accelerators offer performance and efficiency gains by narrowing the scope of acceleration to one algorithmic domain. However, real-life applications are often not limited to a single domain, which naturally makes Cross-Domain Multi-Acceleration a crucial next step. The challenge is, existing FPGA accelerators are built upon their specific vertically-specialized stacks, which prevents utilizing multiple accelerators from different domains. To that end, we propose a pair of dual abstractions, called Yin-Yang, which work in tandem and enable programmers to develop cross-domain applications using multiple accelerators on a FPGA. The Yin abstraction enables cross-domain algorithmic specification, while the Yang abstraction captures the accelerator capabilities. We also develop a dataflow virtual machine, dubbed XLVM, that transparently maps domain functions (Yin) to best-fit accelerator capabilities (Yang). With six real-world cross-domain applications, our evaluations show that Yin-Yang unlocks 29.4× speedup, while the best single-domain acceleration achieves 12.0×.

Making user interaction with laboratory equipment more convenient and intuitive should promote experimental work and help researchers to complete their tasks efficiently. The most common form of interaction in current instrumentation is either direct tactile, with buttons and knobs, or interfaced through a computer, using a mouse and keyboard. Scripting is another function typical of smart and automated laboratory equipment, yet users are currently required to learn bespoke programming languages and libraries for individual pieces of equipment. In this paper, we present two open-source, novel and intuitive ways of interacting with and scripting laboratory equipment. We choose the OpenFlexure family of microscopes as our exemplar, due to their open-source nature and smart control system. Firstly, we demonstrate ‘OpenFlexure Voice Control’ to enable users to control the microscope hands-free. Secondly, we present ‘OpenFlexure Blockly’ which uses the Blockly Visual Programming Language to enable users to easily create scripts for the microscope, using a drag and drop Web interface. We explain the design choices when developing these tools, and discuss more typical use cases and more general applications.

Field-programmable gate array (FPGA) accelerators offer performance and efficiency gains by narrowing the scope of acceleration to one algorithmic domain. However, real-life applications are often not limited to a single domain, which naturally makes Cross-Domain Multi-Acceleration a crucial next step. The challenge is, existing FPGA accelerators are built upon their specific vertically specialized stacks, which prevents utilizing multiple accelerators from different domains. To that end, we propose a pair of dual abstractions, called Yin-Yang, which work in tandem and enable programmers to develop cross-domain applications using multiple accelerators on a FPGA. The Yin abstraction enables cross-domain algorithmic specification, while the Yang abstraction captures the accelerator capabilities. We also developed a dataflow virtual machine, dubbed Accelerator-Level Virtual Machine (XLVM), which transparently maps domain functions (Yin) to best-fit accelerator capabilities (Yang). With six real-world cross-domain applications, our evaluations show that Yin-Yang unlocks 29.4× speedup, while the best single-domain acceleration achieves 12.0×. [ABSTRACT FROM AUTHOR]

Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can run on any system. Current applications that use accelerators, in contrast, are often especially tailored to a specific hardware setup and therefore not universally deployable. This is particularly true for reconfigurable logic as their internal structure requires the circuits and their integration to be designed as well. This makes them inherently difficult to use and therefore less accessible for a general audience. Nevertheless, their balance of flexibility and efficiency puts reconfigurable accelerators in a unique position between CPUs, GPUs, and ASICs. Therefore, one of the main challenges of future heterogeneous systems is to foster collaborative computing between these vastly different components while still being simple to use. Previous approaches mostly focused on subproblems instead of a holistic view of hardware and software in the context of commonplace usability. This paper analyzes the general demands on a reconfigurable platform and derives their requirements regarding accessibility and security. Hereby, we investigate several key features like hardware virtualization, system shared virtual memory, and the use of wide-spread programming paradigms. Then, we systematically build up such a platform based on the established ROCm GPU framework and its internal HSA standard. This new common HERA methodology is finally also demonstrated as a prototype.

We present the OpenFlexure Microscope software stack which provides computer control of our open source motorised microscope. Our diverse community of users needs both graphical and script-based interfaces. We split the control code into client and server applications interfaced via a web API conforming to the W3C Web of Things standard. A graphical interface is viewed either in a web browser or in our cross-platform Electron application, and gives basic interactive control including common operations such as Z stack acquisition and tiled scanning. Automated control is possible from Python and Matlab, or any language that supports HTTP requests. Network control makes the software stack more robust, allows multiple microscopes to be controlled by one computer, and facilitates sharing of equipment. Graphical and script-based clients can run simultaneously, making it easier to monitor ongoing experiments. We have included an extension mechanism to add functionality, for example controlling additional hardware components or adding automation routines. Using a Web of Things approach has resulted in a user-friendly and extremely versatile software control solution for the OpenFlexure Microscope, and we believe this approach could be generalized in the future to make automated experiments involving several instruments much easier to implement.

Designers making deep learning computing more efficient cannot rely solely on hardware. Incorporating software-optimization techniques such as model compression leads to significant power savings and performance improvement. This article provides an overview of DeePhi's technology flow, including compression, compilation, and hardware acceleration. Two accelerators, named Aristotle and Descartes, are designed to achieve extremely high energy efficiency for both client and datacenter applications with convolutional neural network and recurrent neural network, respectively. [ABSTRACT FROM PUBLISHER]

Virtualization has been a well-studied topic for traditional servers. As the demand for the support of virtualization on mobile devices emerged, it again became a popular research topic. However, most research work focused on the applications of mobile virtualization. Detailed knowledge of the characteristics of mobile devices is still lacking. In this paper, we focus on the memory management of mobile virtualization, and propose an optimized page translation oPT with hardware/software co-design. The usage pattern of mobile devices is also considered in the design so it is optimal in terms of the hit ratio of the second stage. The variability of translation time in the second stage is eliminated to provide nearly the same behavior as the non-virtualized architecture. We verify the correctness and feasibility of oPT with a formal proof and a comprehensive evaluation based on both software emulation and hardware implementation. The results indicate oPT can outperform the most popular method. The number of memory accesses is reduced by 51.38 to 56.01 percent, and the average translation time is reduced by 78.63 percent. In addition, the power consumption of the hardware unit in oPT is only about one third that of the traditional method. [ABSTRACT FROM AUTHOR]

Making user interaction with laboratory equipment more convenient and intuitive should promote experimental work and help researchers to complete their tasks efficiently. The most common form of interaction in current instrumentation is either direct tactile, with buttons and knobs, or interfaced through a computer, using a mouse and keyboard. Scripting is another function typical of smart and automated laboratory equipment, yet users are currently required to learn bespoke programming languages and libraries for individual pieces of equipment. In this paper, we present two open-source, novel and intuitive ways of interacting with and scripting laboratory equipment. We choose the OpenFlexure family of microscopes as our exemplar, due to their open-source nature and smart control system. Firstly, we demonstrate 'OpenFlexure Voice Control' to enable users to control the microscope hands-free. Secondly, we present 'OpenFlexure Blockly' which uses the Blockly Visual Programming Language to enable users to easily create scripts for the microscope, using a drag and drop Web interface. We explain the design choices when developing these tools, and discuss more typical use cases and more general applications., (© 2023 The Authors.)

Recent efforts to standardize concurrency semantics for programming languages require programmers to explicitly annotate all memory accesses that can participate in a data race ("unsafe" accesses). This requirement allows the compiler and hardware to aggressively optimize unannotated accesses, which are assumed to be data-race-free ("safe" accesses), while still preserving the intuitive thread interleaving semantics known as sequential consistency (SC). However, unannotated data races are easy for programmers to accidentally introduce and difficult to detect, and thus the safety and correctness of programs can be significantly compromised. The authors argue instead for a safety-first approach, whereby the compiler and hardware treat every memory access as potentially unsafe unless it is proven otherwise. In this way, SC semantics is guaranteed for all programs, whether data-race-free or not. The authors show that the performance and design cost of this approach is insignificant in practice, because the majority of accesses can be proven safe through a simple static or dynamic analysis, and memory ordering constraints can be ignored for such accesses without violating SC. Together with their earlier work on an efficient SC-preserving compiler, their SC hardware provides end-to-end SC semantics at the language level with low overhead. [ABSTRACT FROM PUBLISHER]

The lack of memory safety in languages such as C and C++ is a root source of exploitable security vulnerabilities. This article presents Watchdog, a hardware approach that eliminates such vulnerabilities by enforcing comprehensive memory safety. Inspired by prior software-only mechanisms, Watchdog maintains bounds and identifier metadata with pointers, propagates them on pointer operations, and checks them on pointer dereferences. Checking this bounds and identifier metadata provides both precise, byte-granularity buffer-overflow protection and protection from use-after-free errors, even in the presence of reallocations. Watchdog stores pointer metadata in a disjoint shadow space to provide comprehensive protection and ensure compatibility with existing code. To streamline implementation and reduce runtime overhead, Watchdog uses micro-operations to implement metadata access and checking, eliminates metadata copies via a register renaming scheme, and uses a dedicated identifier cache to reduce checking overhead. [ABSTRACT FROM PUBLISHER]

This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain instructions out of order. Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor and includes out-of-order instruction commit with register and load queue entry release. The commit mode may be switched multiple times during execution. Initial results for a 4-wide processor show that, on average, 52% instructions are committed out of order resulting in 10% to 26% speedups over in-order commit, with minimal hardware overhead. The performance improvement is a result of an effectively larger instruction window that allows more cache misses to be overlapped for both L1 and L2 caches. [ABSTRACT FROM PUBLISHER]

Many modern applications have a significant operating system (OS) component. The OS execution affects various architectural states, including the dynamic branch predictions, which are widely used in today's high-performance microprocessor designs to improve performance. This impact tends to become more significant as the designs become more deeply pipelined and more speculative. In this paper, we focus on the issues of understanding the OS effects on the branch predictions and designing architectural support to alleviate the bottlenecks that are created by misprediction. In this work, we characterize the control flow transfer of several emerging applications on a commercial OS. It was observed that the exception-driven, intermittent invocation of OS code and user/OS branch history interference increased misprediction in both user and kernel code. We propose two simple OS-aware control flow prediction techniques to alleviate the destructive impact of user/OS branch interference. The first consists of capturing separate branch correlation information for user and kernel code. The second involves using separate branch prediction tables for user and kernel code. We demonstrate in this paper that OS-aware branch predictions require minimal hardware modifications and additions. Moreover, the OS-aware branch predictions can be integrated with many existing schemes to further improve their performance. We studied the improvement contributed by OS-aware techniques to various branch prediction schemes ranging from the simple Gshare to the more advanced Agree, Multi-Hybrid, and Bi-Mode predictors. On the 32K-entry predictors, incorporating the OS-aware techniques yields up to 34 percent, 23 percent, 27 percent, and 9 percent prediction accuracy improvement on the Gshare, Multi-Hybrid, Agree, and Bi-Mode predictors, respectively. [ABSTRACT FROM AUTHOR]

We present the OpenFlexure Microscope software stack which provides computer control of our open source motorised microscope. Our diverse community of users needs both graphical and script-based interfaces. We split the control code into client and server applications interfaced via a web API conforming to the W3C Web of Things standard. A graphical interface is viewed either in a web browser or in our cross-platform Electron application, and gives basic interactive control including common operations such as Z stack acquisition and tiled scanning. Automated control is possible from Python and Matlab, or any language that supports HTTP requests. Network control makes the software stack more robust, allows multiple microscopes to be controlled by one computer, and facilitates sharing of equipment. Graphical and script-based clients can run simultaneously, making it easier to monitor ongoing experiments. We have included an extension mechanism to add functionality, for example controlling additional hardware components or adding automation routines. Using a Web of Things approach has resulted in a user-friendly and extremely versatile software control solution for the OpenFlexure Microscope, and we believe this approach could be generalized in the future to make automated experiments involving several instruments much easier to implement., (© 2021 The Authors.)

Current public and private healthcare information technology initiatives have failed to achieve secure integration among providers. Applying the "keep it simple, stupid" principle offers key guidance for solving this problem. [ABSTRACT FROM PUBLISHER]

Heterogeneous parallel computing applications often process large data sets that require multiple GPUs to jointly meet their needs for physical memory capacity and compute throughput. However, the lack of high-level abstractions in previous heterogeneous parallel programming models force programmers to resort to multiple code versions, complex data copy steps and synchronization schemes when exchanging data between multiple GPU devices, which results in high software development cost, poor maintainability, and even poor performance. This paper describes the HPE runtime system, and the associated architecture support, which enables a simple, efficient programming interface for exchanging data between multiple GPUs through either interconnects or cross-node network interfaces. The runtime and architecture support presented in this paper can also be used to support other types of accelerators. We show that the simplified programming interface reduces programming complexity. The research presented in this paper started in 2009. It has been implemented and tested extensively in several generations of HPE runtime systems as well as adopted into the NVIDIA GPU hardware and drivers for CUDA 4.0 and beyond since 2011. The availability of real hardware that support key HPE features gives rise to a rare opportunity for studying the effectiveness of the hardware support by running important benchmarks on real runtime and hardware. Experimental results show that in a exemplar heterogeneous system, peer DMA and double-buffering, pinned buffers, and software techniques can improve the inter-accelerator data communication bandwidth by 2×. They can also improve the execution speed by 1.6× for a 3D finite difference, 2.5× for 1D FFT, and 1.6× for merge sort, all measured on real hardware. The proposed architecture support enables the HPE runtime to transparently deploy these optimizations under simple portable user code, allowing system designers to freely employ devices of different capabilities. We further argue that simple interfaces such as HPE are needed for most applications to benefit from advanced hardware features in practice.

Programs written in languages allowing direct access to memory through pointers often contain memory-related faults, which cause nondeterministic failures and security vulnerabilities. We present a new dynamic tainting technique to detect illegal memory accesses. When memory is allocated, at runtime, we taint both the memory and the corresponding pointer using the same taint mark. Taint marks are then propagated and checked every time a memory address m is accessed through a pointer p; if the associated taint marks differ, an illegal access is reported. To allow always-on checking using a low overhead, hardware-assisted implementation, we make several key technical decisions. We use a configurable, low number of reusable taint marks instead of a unique mark for each allocated area of memory, reducing the performance overhead without losing the ability to target most memory-related faults. We also define the technique at the binary level, which helps handle applications using third-party libraries whose source code is unavailable. We created a software-only prototype of our technique and simulated a hardware-assisted implementation. Our results show that 1) it identifies a large class of memory-related faults, even when using only two unique taint marks, and 2) a hardware-assisted implementation can achieve performance overheads in single-digit percentages. [ABSTRACT FROM AUTHOR]

Hardware acceleration is a widely accepted solution for performance and energy efficient computation because it removes unnecessary hardware for general computation while delivering exceptional performance via specialized control paths and execution units. The spectrum of accelerators available today ranges from coarse-grain off-load engines such as GPUs to fine-grain instruction set extensions such as SSE. This research explores the benefits and challenges of managing memory at the data-structure level and exposing those operations directly to the ISA. We call these instructions Abstract Datatype Instructions (ADIs). This paper quantifies the performance and energy impact of ADIs on the instruction and data cache hierarchies. For instruction fetch, our measurements indicate that ADIs can result in 21–48% and 16–27% reductions in instruction fetch time and energy respectively. For data delivery, we observe a 22–40% reduction in total data read/write time and 9–30% in total data read/write energy. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor. Code is transformed and instructions are generated that run on the PFU using a co-designed virtual machine (Cd-VM). Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 29% in SPECFP and 19% in SPECINT, and up-to 55%, over modern out-of-order processor. [ABSTRACT FROM PUBLISHER]

Proposals have focused on reducing energy requirements for large-scale computing facilities (LSCFs), but little research has addressed the need for energy-usage-based accounting. Energy-aware accounting and billing benefits LSCF owners and users. This article makes a case for accurate cost accounting and billing, which accounts for user-specific energy usage, and identifies the hardware- and software-level changes necessary to support energy-aware accounting. [ABSTRACT FROM PUBLISHER]

This article evaluates the scalability and productivity of six parallel programming models for heterogeneous architectures, and finds that task-based models using code and data annotations require the minimum programming effort while sustaining nearly best performance. However, achieving this result requires both extensions of programming models to control locality and granularity and proper interoperability with platform-specific optimizations. [ABSTRACT FROM PUBLISHER]