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The sweep frequency response analysis (SFRA) technique is based on measuring the power transformer electrical transfer functions over a wide frequency range to identify the abnormal areas prior to serious failure. This study presents the proposed diagnostic adjusted R‐square technique to identify the transformer faults using the SFRA technique. The SFRA measurements are ranged up to and beyond 1 MHz. The proposed technique is used to calculate the relative factor for adjusted R‐square coefficient between the actual data and new measurement data sets. The results of the proposed method are evaluated and compared with existing Chinese Standard factor DL/T 911‐2016 and CCF factor of IEEE Std. C57.149™ Standard indicates that the suggested methodology is more reliable to identify and analyse the internal faults of the transformers. This technique is considered to be effective indicator to predict the internal physical condition inside the transformer, which moves the field forward. [ABSTRACT FROM AUTHOR]

The active clamp flyback (ACF) converter utilising gallium nitride (GaN) devices with high‐switching frequency and high efficiency is impressive in system miniaturisation for AC–DC adapters. Owing to poor reverse conduction of GaN devices, the improper dead time between two switches can cause large power consumption in high frequency. This study proposes a dynamic dead time optimisation technique for GaNs ideal zero‐voltage switching (ZVS) to address the issue. It adjusts the clamp switch on time to avoid large reverse conduction voltage stress on the main switch in different loads conditions. In addition, a new control scheme for clamp switch is introduced for enhancing efficiency in light to medium load. These techniques are experimentally verified on a 45 W (20 V/2.25 A) prototype of an ACF converter with a field‐programmable gate array. The controller enables the system to operate at 1 MHz and dynamically modulates the dead‐time under universal input and full load. With the light load ZVS control scheme, the system can achieve a maximum efficiency of 94.12 and 80.23% in the worst case. The prototyped converter can achieve power density (exclude case and controller) of 18 W/in3. [ABSTRACT FROM AUTHOR]

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel‐metal‐oxide‐semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post‐layout are commensurate with pre‐layout. Post‐layout simulation results show that when temperature changes from − 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from − 78 to −72dB at 1 MHz for 0.2 VPP input signal, −3 dB bandwidth changes from 2.5 to 5 GHz, input‐referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW. [ABSTRACT FROM AUTHOR]

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz. [ABSTRACT FROM AUTHOR]

Electric vehicle (EV) battery chargers operate from moderate switching frequency (MSF) to high switching frequency (HSF) to achieve high power density. To operate the HSF power electronic devices, the selection of gate drivers and its associated components is crucial. Laboratory developed gate driver circuits (GDCs) often fail to drive these HSF devices adequately due to noise vulnerability, PWM duty loss and common-mode currents. Further, at MSF and HSF ranges, the gate-to-source terminals of the device are subjected to high voltages due to unwanted noise resulting in false turn-on of the switch leading to the converter failure. In this paper, firstly, an improved GDC and it's associated component selection criteria are proposed for HSF EV application. The proposed GDC is simple in structure with minor components; thus, it is cost-effective and highly reliable. Secondly, the proposed GDC is compared with the other commercially available competent GDCs. Power losses, cost and dynamic switching performance are the figures-of-merit for the quantitative assessment. From the comparison, it will be shown that the proposed GDC exhibits an overall superior performance among the popular GDCs. Finally, the distinctive features of the proposed GDC are experimentally validated for several test cases and the obtained results are presented. [ABSTRACT FROM AUTHOR]

This paper presents a capacitive power transfer (CPT) system design for low-power rotary applications. The aim of a rotary CPT system is to be free of power cables so it can achieve 360 degrees of free rotation, while remaining simple and easy to clean. In this work, a class-E high-frequency inverter with second-order LC compensation is proposed to drive the rotary CPT system. An LC compensation circuit is applied on both stationary and rotating sides in order to maximise the power transfer by increasing the voltage across the coupling plates. By implementing the proposed technique, the Class-E LCCL rotary CPT system that is efficient and less sensitive to load variations can be achieved. A Boost converter is also proposed here to provide input impedance matching and tune the input power of the Class-E LCCL rotary CPT system. A 10 W multiple plate rotary CPT prototype based on cascaded Boost- Class E LCCL is designed and implemented to demonstrate efficient wireless power transfer (WPT) across the rotating load. The results reveal >76% power transfer efficiency is successfully achieved at 1 MHz operating frequency and with 7.67 W output power.

This study presents a newly developed modular system for control of power electronic amplifiers in high-power, high-frequency power hardware in the loop experiments. The proposed design comprises computational nodes connected via multi-gigabit fibre-optic links. Nodes are modular and reconfigurable, allowing interfacing with a range of sensors and actuators, typically voltage and current sensors, and switching converters. The system has been designed for scalability to permit arbitrarily high power ratings and fidelity to be achieved through paralleling and interleaving of multiple power converter modules, targeting an ultimate sample and control rate of 1 MHz. Experimental validation is presented using a two-node configuration to facilitate a power electronic experiment operating at 120 V(rms) and 10 A(rms), with a fundamental frequency of 50 Hz and frequency content up to the 11th harmonic.

In this work, a DVCO has been designed for a 4‐bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi‐objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC. [ABSTRACT FROM AUTHOR]

This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12‐bit 200 MS/s replica driving pipelined analogue‐to‐digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5‐bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front‐end sample‐and‐hold (S/H) circuit, and the transconductance (gm) of the inner source follower is maximised by increasing the current and threshold voltage (VT) reduction. Replica input sampling networks are designed for the first‐stage sub‐ADC and the first‐stage MDAC with different aspect ratios to minimise the sampling skew for the S/H‐less architecture. A prototype 12‐bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious‐free dynamic range (SFDR) and signal‐to‐noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

This article proposes a wideband ΔΣ fractional‐N frequency synthesiser (WBFS) for software‐defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low‐power mode for the low‐power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide‐by‐two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2‐V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low‐power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low‐power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low‐power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range. [ABSTRACT FROM AUTHOR]

This study presents a newly developed modular system for control of power electronic amplifiers in high-power, high-frequency power hardware in the loop experiments. The proposed design comprises computational nodes connected via multi-gigabit fibre-optic links. Nodes are modular and reconfigurable, allowing interfacing with a range of sensors and actuators, typically voltage and current sensors, and switching converters. The system has been designed for scalability to permit arbitrarily high power ratings and fidelity to be achieved through paralleling and interleaving of multiple power converter modules, targeting an ultimate sample and control rate of 1 MHz. Experimental validation is presented using a two-node configuration to facilitate a power electronic experiment operating at 120 Vrms and 10 Arms, with a fundamental frequency of 50 Hz and frequency content up to the 11th harmonic. [ABSTRACT FROM AUTHOR]

This paper presents a capacitive power transfer (CPT) system design for low-power rotary applications. The aim of a rotary CPT system is to be free of power cables so it can achieve 360 degrees of free rotation, while remaining simple and easy to clean. In this work, a class-E high-frequency inverter with second-order LC compensation is proposed to drive the rotary CPT system. An LC compensation circuit is applied on both stationary and rotating sides in order to maximise the power transfer by increasing the voltage across the coupling plates. By implementing the proposed technique, the Class-E LCCL rotary CPT system that is efficient and less sensitive to load variations can be achieved. A Boost converter is also proposed here to provide input impedance matching and tune the input power of the Class-E LCCL rotary CPT system. A 10 W multiple plate rotary CPT prototype based on cascaded Boost- Class E LCCL is designed and implemented to demonstrate efficient wireless power transfer (WPT) across the rotating load. The results reveal >76% power transfer efficiency is successfully achieved at 1 MHz operating frequency and with 7.67 W output power. [ABSTRACT FROM AUTHOR]

This study introduces the generalised canonical transfer function (TF) of the band‐pass negative group delay (NGD) circuit. The principle to identify the unfamiliar band‐pass NGD circuits is suggested. Similar to the filter theory, the band‐pass NGD TF can be established from low‐pass to band‐pass frequency transform. The fundamental characteristics of the NGD topology are described. The canonical TF feasibility is concretised with the second‐order equivalent impedance constituted by passive elements. The synthesis formulas in function of the desired NGD level and bandwidth are analytically established. Application examples of band‐pass NGD impedance synthesis, designed and fabricated are proposed as a proof of concept. Prototypes of band‐pass NGD circuits with centre frequencies 1 and 1.5 MHz for the targeted group delay optimal values, respectively, −1 and −1.5 µs are designed and fabricated. As expected, band‐pass NGD results in good agreement with the theoretical prediction were obtained with simple lumped circuits. In the future, thanks to theory simplicity, the NGD band‐pass cell can be potentially useful for the signal delay correction. [ABSTRACT FROM AUTHOR]

This study presents the design and experimental characterisation of single‐layer solenoid air‐core inductors. The analytical expressions for the winding inductance, self‐capacitance, and winding resistance are derived. The inductor properties are analysed up to the first self‐resonant frequency. The procedure to design air‐core inductors for high‐frequency (HF) applications is provided. Experimental validations of the analytical equations are given. A single‐layer air‐core 20μH inductor was designed, built, and measured. The bandwidth of the designed inductor obtained from theoretical predictions was about 100 MHz. The measured quality factor was 181 at 1 MHz. The results of this study are useful for engineers and designers in the areas of power supplies, datacentres, radio‐frequency power amplifiers, radio‐frequency transmitters, and HF filters. [ABSTRACT FROM AUTHOR]

This Letter presents a millimetre-wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of ${-98}\,{\rm dBc/Hz}$−98dBc/Hz at 1 MHz offset frequency and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ${\sim }{9000}\,{\rm \mu} {\rm m}^2$∼9000μm2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology. [ABSTRACT FROM AUTHOR]

A novel feedforward‐coupling ring oscillator (FRVCO) is presented. A comparative study in terms of oscillation frequency and phase noise is conducted between the proposed model and the traditional FRVCO. Due to the improved delay cell, high oscillation frequency, low phase noise and uniform multi‐phase output can be achieved. Compared with the traditional FRVCO, under the same design parameters, the FRVCO proposed in this Letter can increase the oscillation frequency by 10% while reducing the phase noise at 1 MHz by at least 10 dB. [ABSTRACT FROM AUTHOR]

A multiphase all‐digital crystal‐less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10‐phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time‐to‐digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from − 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and − 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm2 in a 65‐nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system. [ABSTRACT FROM AUTHOR]

This paper presents reconfigurable and hardware‐efficient VLSI architecture of time domain cyclostationary‐feature detector (TCD) for spectrum sensing in the cognitive‐radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE‐Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware‐efficient techniques have been introduced for the multiply‐&‐accumulate and accumulator architectures of suggested TCD design. Real‐world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post‐layout simulation of the proposed detector have been performed using 65 nm‐CMOS technology and it occupies 0.32 mm2 of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state‐of‐the‐art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively [ABSTRACT FROM AUTHOR]

This Letter presents a digital low‐dropout regulator (LDO) that achieves fast transient response with a flash ADC‐based parallel comparison. A non‐linear decoder is employed in the flash ADC to further enhance the transient response. In the design of the power switch array, an exponential‐ratio array (ERA) is adopted for high load driving capacity. The proposed digital LDO implemented in 65‐nm CMOS achieves a load range of 0.04–82.7 mA when the input voltage and the output voltage are 1.0 and 0.9 V, respectively. The digital LDO achieves a settling time of 6 μs with a load step of 48 mA, exhibiting the state‐of‐the‐art normalised settling time for the clock frequency of 1 MHz. [ABSTRACT FROM AUTHOR]

This Letter presents an inverter‐type time amplifier (TA)‐based phase noise filter (TAPNF) with 8 dB phase noise suppression and −133 dBc/Hz phase noise sensitivity at 1 MHz offset. The phase noise improvement strategy, low noise TA design and power consumption reduction techniques are presented. The TAPNF is fabricated in a 65 nm CMOS process with 1.4 mm × 1.6 mm chip area and consumes 50 mW power. To authors' best knowledge, the TAPNF achieves the best phase noise and figure‐of‐merit compared with state‐of‐the‐arts with similar technologies and carrier frequencies. [ABSTRACT FROM AUTHOR]

A new wide‐input dynamic range flip‐flop capable of operation at an ultra‐low supply voltage of 0.16 V is presented. The proposed flip‐flop named as capacitively boosted sense‐amplifier flip‐flop (CB‐SAFF) utilises a capacitively boosted sense‐amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB‐SAFF outperforms existing state‐of‐the‐art sense‐amplifier flip‐flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB‐SAFF can also sample low‐swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra‐low voltage Internet of Things, wireless sensor nodes and smart motes. [ABSTRACT FROM AUTHOR]