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The chaotic systems are one of the most important areas that increasing the popularity and are actively used in several fields. One of the most essential structures in chaotic systems is chaotic oscillator which generates chaotic signals. IQ-Math and floating point number systems are one of the preferred number standards. Presented in this study, the Modified Chua chaotic oscillator has been designed to work on FPGA chips using fixed point and floating point number systems. Euler numeric algorithm has been used for the design of the Modified Chua chaotic oscillator. The first section of the study, Modified Chua chaotic system based on fixed point has been composed the model in the Matlab Simulink and transformed to VHDL with the help of Matlab HDL Coder Toolbox. The second section of the study, Modified Chua chaotic oscillator has been designed with VHDL based on floating point. Modified Chua chaotic oscillators which are composed with two different number standards have been tested using Xilinx ISE Design Tools in VHDL. Modified Chua chaotic oscillators which have two different numbers standards and designed, are synthesized for Virtex-6 on ML605 FPGA development board with Xilinx ISE Design Tools 14.2 program. Values that are achieved from the process of synthesizing and maximum operating frequency have been presented. As a result, the study has obtained that fixed point number standard maximum operating frequency is 50.242 MHz and floating point number standard maximum operating frequency is 273.631 MHz.

The chaotic systems are among the most important areas that have increased in popularity and are actively used in several fields. One of the most essential components in chaotic systems is the chaotic oscillator which generates chaotic signals. IQ-Math and floating point number systems are preferred number standards. In this study, the Modified Chua chaotic oscillator has been designed to work on FPGA chips using fixed point and floating point number representations, and both system version performances are compared. Euler numeric algorithm has been used to design the Modified Chua chaotic oscillator. In the first section of the study, the Modified Chua chaotic system based on fixed point has been composed the model in the Matlab Simulink and converted to VHDL with the help of Matlab HDL Coder Toolbox. In the second section of the study, the Modified Chua chaotic oscillator has been designed with VHDL based on floating point. Modified Chua chaotic oscillators which are composed with two different number standards have been tested using Xilinx ISE Design Tools in VHDL. Modified Chua chaotic oscillators which have two different number standards and designed, are synthesized for Virtex-6 on ML605 FPGA development board using Xilinx ISE Design Tools 14.2 program. The values that are achieved from the process of synthesizing and the process of maximum operating frequency have been presented. As a result, the study has found that fixed-point representation achieved a maximum operating frequency of 50.242 MHz, while the floating-point representation achieved 273.631 MHz. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a method for emulating switch-level models of CMOS circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. The method presented in this paper, unlike the abstraction methods, can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the remaining parts of the circuit are emulated at the gate-level. The experimental results show that the presented emulation-based approach could be significantly faster than existing simulation-based approaches. The analytical performance estimation shows that the speed-up grows with the circuit size and is workload dependent. [Copyright &y& Elsevier]