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Dielectric breakdown (BD) is known to cause component failure in electronic devices and high‐voltage power lines over many decades. In recent years, this failure mechanism has been exploited to intentionally form nanoscale filaments in resistive random‐access‐memory (ReRAM) devices for artificial intelligence (AI). The statistical nature of this failure mechanism, known as the inverse size scaling law based on the weakest‐link theory, dictates the ever‐higher forming voltages for ReRAM devices, in turn, requiring additional peripheral transistors. This law also causes diminishing lifetimes of electronic components for future generations of very‐large‐integrated circuits (VLSI) technology. Currently, the semiconductor industry faces these scaling barriers limiting the miniaturization of both VLSI and AI hardware technology. Here, experimental evidence of a reverse area dependence is presented by introducing an innovative fabrication process with a hydrogen‐plasma‐treated layer in a bilayer HfO2 structure. Using joint order statistics rather than traditional extreme‐value statistics, a physics‐based statistical model is developed in agreement with the experimental data, thus demonstrating that there is no fundamental reason preventing this law from being reversed or altered. These findings will have a significant impact on both technology scaling and fabrication innovation for electronic and/or bioinspired nanomaterials; moreover, stimulate much research in physics, statistics, and reliability. [ABSTRACT FROM AUTHOR]

Abstract Dielectric breakdown (BD) is known to cause component failure in electronic devices and high‐voltage power lines over many decades. In recent years, this failure mechanism has been exploited to intentionally form nanoscale filaments in resistive random‐access‐memory (ReRAM) devices for artificial intelligence (AI). The statistical nature of this failure mechanism, known as the inverse size scaling law based on the weakest‐link theory, dictates the ever‐higher forming voltages for ReRAM devices, in turn, requiring additional peripheral transistors. This law also causes diminishing lifetimes of electronic components for future generations of very‐large‐integrated circuits (VLSI) technology. Currently, the semiconductor industry faces these scaling barriers limiting the miniaturization of both VLSI and AI hardware technology. Here, experimental evidence of a reverse area dependence is presented by introducing an innovative fabrication process with a hydrogen‐plasma‐treated layer in a bilayer HfO2 structure. Using joint order statistics rather than traditional extreme‐value statistics, a physics‐based statistical model is developed in agreement with the experimental data, thus demonstrating that there is no fundamental reason preventing this law from being reversed or altered. These findings will have a significant impact on both technology scaling and fabrication innovation for electronic and/or bioinspired nanomaterials; moreover, stimulate much research in physics, statistics, and reliability.

This work focused on the effects of electroforming ambient temperature and annealing process on the metal oxide multilayer switching resistive random access memory (RRAM) device. We developed Pt/HfO2/TiO2/HfO2/Pt RRAM cells with annealing and without annealing process. Annealed devices are electroformed at a high ambient temperature 80 °C (A-80). Non-annealed devices are electroformed at low atmosphere temperature 25 °C (NA-25). We investigate the outcomes of NA-25 and A-80 devices. Results confirmed that annealed and high ambient temperature formed devices (A-80) contribute to the low operating voltage, improved uniformity, and reliability compared to NA-25 device. [ABSTRACT FROM AUTHOR]

Herein, we characterize resistive random access memory (RRAM) devices containing an oxygen-deficient layer. The RRAM devices consist of multiple layered NiO thin films that consist of an oxygen-deficient NiO 0.95 layer, within a NiO/NiO 0.95 /NiO layer structure. The NiO thin-film layers were deposited on Pt/Ta/SiO 2 /Si substrates by radio frequency magnetron sputtering. The stoichiometry and thickness of the NiO triple-layer thin films were determined by Auger electron spectroscopy. We fabricated RRAM capacitors with a structure of Pt/NiO/NiO 0.95 /NiO/Pt to investigate the resistive switching characteristics. The presence of an oxygen-deficient layer significantly lowers the forming and SET/RESET voltages compared to a Pt/NiO/Pt RRAM capacitor. This reduces the energy required to form conducting filaments in the oxygen-deficient layer. Moreover, the forming and SET/RESET voltages exhibit reduced dispersion due to the relatively high oxygen vacancy density in the oxygen-deficient NiO 0.95 layer. [ABSTRACT FROM AUTHOR]

In conventional HfO2-based resistive random access memory (RRAM), SiO2 is usually adopted as side wall spacer (low-k spacer) to define the device feature size. It is found that the forming voltage of the conventional HfO2 RRAM with SiO2 spacer rises when the device size is scaling down from 16.0 μm2 to 0.16 μm2, which is detrimental for application of high density HfO2-based RRAM. In this study, a high permittivity side wall spacer (high-k spacer) Ta2O5 is introduced to replace SiO2 spacer. The Ta2O5 side wall effectively suppress the forming voltage rising issues during RRAM device scaling without introducing costly processing steps. Moreover, compared to the conventional HfO2-based RRAM, the side wall enhanced device exhibits faster switching speed, smaller operation voltage, and higher reliabilities, including endurance and retention. As a result, the use of Ta2O5 side wall significantly enhances the overall switching characteristics of the HfO2-based RRAM device.

In this paper, we discover an operation method that can effectively decrease the forming voltage in resistance random access memory (RRAM). Forming voltage can be reduced by either increasing the rising time of the forming-waveform or by increasing the temperature in the forming process. However, the resulting electronic RRAM characteristics after each of these methods differ. While increasing the rising time causes greater damage to the switching layer due to longer accumulation of charge, increasing temperature in the forming process does not. The high temperature-formed RRAM excels in retention and endurance tests, proving an effective means to decrease forming voltage.

This letter introduces a method of using bipolarity bias voltages in the forming process to effectively reduce the forming voltage of a one-transistor and one-resistance random access memory device. A bipolar incremental-step-pulse programming process is applied, and a complete operation pulse for the forming process is described. This method reduces forming voltage without any cost to the device performance, and the device maintains good reliability. The likely physical mechanism of this bipolar operation is also presented based on the measured electrical characteristics. [ABSTRACT FROM PUBLISHER]

In this study, VO3 have been successfully fabricated for application in resistive random access memory (RRAM). The RRAMs with V2O5 and Sm2O3 films have shown bipolar switching characteristics. Introducing a suitable oxygen concentration in the V2O5 film can improve the switching performance. Postannealing of the V2O5/Sm2O3/TiN/SiO2/Si device can decrease the forming voltage to 1.1 V. [ABSTRACT FROM AUTHOR]

In this study, the rising forming voltage issue during device cell scale-down in resistance random access memory (RRAM) is solved by introducing new high-permittivity (high- k) material as the side-wall spacer structure, unlike the normally used low-permittivity (low- k) material. Simulated electrical fields based on COMSOL Multiphysics software results suggest a RRAM device with a high- k spacer effectively confines the electric field. The effects of this confined electric field are notable, especially when the device cell is scaled down. The device fabrication process is modified to incorporate the high- k sidewall. Cross-sectional transmission electron microscopy imaging confirms the existence of SiO2 and HfO2 as the spacer structures in two different devices. Electrical measurements of forming voltages ranging from 1 to 0.16 µm2 are conducted to verify the effects. Statistical measurements confirm that the forming voltages of the devices with high- k material as sidewall do not increase with a reduction in device cell size. Moreover, reliability tests, including endurance and retention for the high- k sidewall device, also exhibit very stable resistance switching characteristics. As a result, the structure that is proposed successfully solves the forming voltage issues within small device cells in RRAM without any cost to device reliability. [ABSTRACT FROM AUTHOR]

We report the reproducible unipolar resistance switching behavior in Pt/SnFe 2 O 4 /Pt structures. The amorphous SnFe 2 O 4 thin film was spin-coated on the Pt/TiO 2 /SiO 2 /Si substrate by a sol-gel method. The current-voltage characterization showed that as the spin coating cycles increased, the resistive switching (RS) characteristics became stable, and an excellent RS performance showing uniform set voltage distribution, stable resistance of both low resistance and high resistance states, and narrow reset current distribution can be obtained in SFO films with a thickness about 220 nm. Based on the conducting filament model, the variation of the RS behavior was ascribed to the increase of the electroforming voltage in the thicker films, which consequently induced more oxygen vacancies to participate in the RS process. Our results indicated that the electroforming voltage performs a significant role in the RS properties of the amorphous SnFe 2 O 4 and the optimized RS behavior through the regulation of preparation process can be used for the resistance random access memory applications. [ABSTRACT FROM AUTHOR]

Based on probability analysis, this letter presents a simplified analytical model for the area and thickness scaling of forming voltage of resistive switching memories. The model is validated by experimental data and enables forming voltage projection. A switching resistor network model is employed to simulate the statistical distributions of forming voltage, which also confirms the analytical model. The increase of forming voltage at decreasing device area is undesirable for memory scalability. Local field enhancement may help to reduce both the magnitude of forming voltage and its area dependence. [ABSTRACT FROM PUBLISHER]

A rising forming voltage issue with scaling‐down resistive random access memory (RRAM) device cells is successfully solved by introducing new high‐permittivity (high‐k) material as the side‐wall spacer structure. As reported by Ting‐Chang Chang, Kuan‐Chang Chang, and co‐workers in article number 1700171, both COMSOL‐simulated electrical field and electrical measurements confirm the confined the electrical field by the surrounded high‐k spacer. The cross section views clearly show the different structures with a spacer. [ABSTRACT FROM AUTHOR]