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The time required for testing silicon defects continues to rise as design complexity and transistor count increases in-line with Moore’s Law. Structured test, particularly scan compression, assists with reducing the amount of time and effort involved. Furthermore, the associated design-for-test (DFT) is often reusable for determining the root cause of defective silicon behavior. However, new challenges associated with higher system integration, such as 3D-IC and chiplet packaging technologies, and shrinking time-to-market, requires a new approach to achieve low defect levels and gain understanding of defective or abnormal behavior This relatively new approach is known as Silicon Lifecycle Management (SLM) and enables testing and analysis throughout the different silicon life phases, and utilized analytics (diagnostics) to improve each phase from design to in-field operation. This presentation covers a discussion on SLM that is built on in-chip environmental, structural, and functional monitors and can leverage DFT hardware to enable deep insights from silicon die to assembled systems. We discuss the similarities to a structured manufacturing test flow such as implementation, data acquisition from the silicon, analytics on the data, and corresponding corrective action. Additionally, key differences are pointed out, especially regarding real-time or in-situ operational requirements. Data is gathered at every opportunity during the device lifecycle providing continuous analysis and actionable feedback. With respect to test methods such as stored manufacturing test patterns or built-in-self test, SLM extends the ability to test beyond die and package phases, enabling testing silicon throughout its life cycle.

In last decade, SiGe BiCMOS technologies open a new cost-efficient market first at mm-wave frequencies, then at sub-THz and THz range. Starting with the commercial use of automotive radars at 77 GHz, and the demand for 120/140 GHz radars, the market now has a strong interest on low-cost silicon based technologies for such high frequencies. The driving force behind the BiCMOS is not anymore only radar applications but also 5G/6G communication systems, operating at 60, 140 or even 240/300 GHz. Furthermore, the strong need on the driving circuitries of photonics components has created a mass market of high speed communication circuitries. The latest developments on SiGe HBTs with fmax of beyond 700 GHz boosts the research and development effort on circuit and system area to take share from the new markets. In parallel to the developments on SiGe HBT performance, “More-than- Moore” path, which covers all the additional functionalities to the standard CMOS process (i.e. MEMS devices, microfluidics, photonics, etc…), allows to realize multi-functional circuits and systems. Heterogeneous integration as a key and enabler technology for the multi-functional systems has also great importance these days. Hetero integration of different technologies such as high scaled CMOS, SiGe BiCMOS or even III-V ones has become real. Such integration of multi-chip technologies provides the highest performance with the most efficient size and power consumption; thus paves the way for next generation smart systems integration. In this talk, approaches used for the integration of different More-than-Moore modules into a BiCMOS process will be presented. New hetero-integration technologies and corresponding challenges will be discussed.

The widespread usage of Long Short-Term Memory (LSTM) accelerators in time-series related applications necessitates using a protection mechanism against faults caused by wear-out and environmental effects. This paper proposes a Concurrent Error Detection (CED) scheme combining low overhead duplication and residue codes to detect faults in multiply and add stages of LSTM accelerators. For the multiply stage, the CED consists of a multiplier for every LSTM multiplier with a temporal selection of data. For the add stage, the CED adders are shared among the LSTM adders, thus spatial selection is performed. The experimental results show that the proposed method yields good detection probability with a lower area and power overhead in comparison with the traditional duplication techniques that indiscriminately duplicate all hardware structures all the time.

Common Mode Transient Immunity (CMTI) is one of the most important key parameters of an isolator. CMTI describes the ability of an isolation barrier to withstand fast common mode transients applied between two isolated circuits and thus to maintain the system integrity. To measure the CMTI, very fast voltage changes between the two isolated circuit grounds must be generated. This paper presents a novel method to generate the transients and measure the CMTI. A DC-DC converter is used with a high voltage switch in addition to an appropriate regulation circuit using only passive elements to generate the desired voltage level and slope. The method was implemented on an evaluation board to evaluate a few commercial digital isolators. Measurement results are presented and discussed.

The high distribution of the manufacturing of Integrated Circuits (ICs) over different foundries yields long and untrustworthy supply chains. Logic locking is one prominent protection technique against malicious usage and counterfeit. The emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has recently been utilized to implement new polymorphic logic mechanisms to protect intellectual property. The mechanisms’ assessment is important to reinforce the newly introduced protection mechanism and, hence, avoid any weak logic structures. So far, approximate Hamming Distance-based assessment techniques have been used for determining the protection quality while considering combinatorial circuits only. This work proposes a novel method to assess the quality of the RFETbased logic locking structures for sequential circuits. In particular, formal techniques are orchestrated to analyze the circuit’s state space to determine whether any incorrect keys exist that unintentionally unlock and exhibit the circuit’s correct functional behavior. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.

Boosting hardware design productivity is a major plus of SpinalHDL, a Scala-based Hardware Description Language (HDL). SpinalHDL achieves this by providing object oriented programming, functional programming, and metahardware description finally enabling the generation of Verilog code. Despite all the advantages of SpinalHDL, verification is the biggest challenge here as well. In this paper, we bring Coverage-Guided Fuzzing (CGF), a wellestablished software testing technique, to the SpinalHDL design flow. We have implemented our approach SPINALFUZZ on top of the fuzzer AFL++. We leverage Scala-features to automate as many tasks as possible and ease the integration of fuzzing in SpinalHDL. In the experiments we demonstrate the effectiveness of SPINALFUZZ in comparison to Constrained Random Verification (CRV). For a wide range of SpinalHDL designs we show that SPINALFUZZ outperforms CRV and reaches coverage-closure.

Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.

IEEE 1687-2014 gained traction in the test community very fast. Numerous innovations, publications, and implementations have been described, from both, industry and academia. Today, 7 years plus a few months after the release of the standard, much of the commercial test infrastructure is based on IJTAG. It is supported by all three major EDA tool vendors. In addition, derivatives of IEEE 1687, namely IEEE P1687.1 and P1687.2 are in active development. This is not to say that the original IEEE 1687 standard is without flaws. The 1687 working groups has actively collected not only errata, but also requests from users and tool developers alike, asking for upgrades to the standard, if it ever will be reopened. This time has finally come. In January 2022, Jeff Rearick had submitted a modified PAR, initiating the process. This PAR was subsequently approved, and with that, the P1687 is now officially open for upgrades.

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress. In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity. Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.

This paper presents a powerful combination of Analog Mixed-Signal (AMS) verification in combination with emerging IEEE P1687.2 standard, capable of enabling automation of the large part of test pattern generation flow from the specification to Automatic Test Equipment (ATE). The inherent property of AMS verification to incorporate UVM based environment and a configuration with design modules described at arbitrary abstraction levels allows efficient pre-silicon test setup simulation. UVM also facilitates automated generation of STIL, used as the main vehicle to trigger various ATE instruments. The approach is piloted on a power amplifier product that contains BigA and notso- small D portion. To the best of our knowledge, this is the first proposed self-containing flow that achieves test development reduction and provides guidance for test quality improvement while relying entirely on emerging and existing IEEE standards.

High-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are diagnosed hierarchically; first, their location, then their nature (i.e., static or dynamic), and finally, their functional fault model. The HMD approach leads to a more accurate diagnostic, enabling the precise identification of yield loss causes.

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISCV processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

We introduce a methodology to predict degradation in an SoC device undergoing a thermally accelerated aging process. SoCs are usually stressed at high temperatures and voltages (above nominal) to accelerate their aging so that their reliability under nominal conditions can be predicted. Here we focus on the thermal acceleration process. We implement a ring oscillator-based test structure and consider its free-running frequency as our reference parameter to measure degradation. We analyze 500 hours of BTI-induced degradation behavior at different temperatures and observed that the final degradation can be confidently predicted from the measurements in first half of the experiment. This observation provides a new research avenue to predict reliability test results, such as HTOL, which lasts for 1000 hours and has a negative impact on the product’s time to market.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

Failure diagnosis is a software-based data-driven procedure. Collecting an excessive amount of fail data not only increases the overall test cost, but may also lead to degradation of diagnostic resolution. Test-termination prediction is thus proposed to dynamically determine which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. In this work, we describe a novel data-model co-design method of using deep learning method for efficient test-termination prediction. In particular, images describing the failing test responses are constructed from failure-log files. A multi-layer convolutional neural network (CNN) embedding a residual block is then trained, based on the images and known diagnosis results. The learned CNN model is later deployed in a test flow to determine the optimal test-termination for an efficient and quality diagnosis. Experiments on actual failing chips and standard benchmarks demonstrate that the proposed method outperforms SOTA works. Our method creates opportunities to harness the power of deep learning for improving diagnostic efficiency and quality.

Digital signature is a key security technology for authenticating systems and devices, thus enabling the existence of wide collaborative environments. This is also true for safetycritical systems that are constrained by strict performance requirements. Such applications are usually implemented through Multi-processors System-on-Chip (MPSoC). The dawn of quantum computing represents a threat for current cryptography, including the digital signatures. In order to prepare for such an event, electronic systems must integrate quantum-secure (postquantum) cryptography. Dilithium is one of the main alternatives for practical implementation of post-quantum signatures. While most of the attention has been given to the security analysis and single-core software implementation, the Dilithium MPSoC exploration for high performance has been neglected. To this end, this work presents two contributions. First, the design and exploration of optimized Dilithium multi-core implementations. Second, the deployment of Dilithium on real life MPSoCs used in automotive applications and operated with a commercial RTOS. Results show that Dilithium can be efficiently implemented and optimized on a multicore architecture, improving the performance up to 48% for key generation, 34% for signature and 42% for verification when compared to single core solutions.

Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications. Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high precision and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.

Emergence of Deep Neural Networks (DNN) has led to a proliferation of artificial intelligence applications. Although applications of DNNs to real-world problems have become ubiquitous, there is a lack of understanding of how these circuits are affected by faults. Due to this fact, adoption of DNNs in safety-critical domain has been lagging behind. As there exist no commonly accepted reliability assessment metrics for DNNs, their certification for safety-critical applications is not possible. In this PhD thesis, we are optimising the fault injection process that is a widely used reliability assessment technique for DNNs.

While the importance of parallel hardware architectures has been increasing over the decades, software tends to be one step behind. In the testing and reliability field, noncommercial software is often designed with few to no parallelism in mind. In this paper, we focus on a toolchain that allows us to measure the stress metrics of large SoC through the analysis of enormous Value Change Dump files produced by the testing and simulation equipment. In this toolchain, we concentrate on speeding up the analysis and making the entire process more automatic through pipeline and parallelization techniques. We tested the resulting Burn-In test application on a real chip, developed by STMicroelectronics.

In this work, a comparative study between established Control Flow Checking (CFC) techniques is presented. A novel test bench is used to inject permanent falts into an emulated microcontroller. This test bench manages all the assessment phases, from fault generation to fault injection to results classification. Results are presented comparing the attained results in terms of the ability to detect permanent faults.

Currently, Deep learning and especially Convolutional Neural Networks (CNNs) have become a fundamental computational approach applied in a wide range of domains, including some safety-critical applications (e.g., automotive, robotics, and healthcare equipment). Therefore, the reliability evaluation of those computational systems is mandatory. The reliability evaluation of CNNs is performed by fault injection campaigns at different levels of abstraction, from the application level down to the hardware level. Many works have focused their effort on evaluating the reliability of neural networks in the presence of transient faults. However, the effects of permanent faults have been investigated at the application level, only, e.g., targeting the parameters of the network. This paper presents the ongoing work on the reliability evaluation of CNNs targeting permanent faults in GPU devices, considering different fault injections levels. Our preliminary results show that the fault injections performed at the application level generate more optimistic results than considering an architectural level fault injection.

The technology evolution has tried to address the demand for faster computers. Despite the achieved speed-up in terms of memory and computation performances, the communication between the memories and the processor remains a bottleneck. The Computation in-Memory (CIM) aims to solve this problem by moving the computation directly inside the memory. This study focuses on the Logic-In-Memory (LIM), which represents the applications that accelerate Boolean Logic. This paper introduces the analysis of selected Logic-In-Memory operations simulated under various operating conditions. This is the preliminary step to study the behavior of LIM for security applications.

Memory requirements are constantly increasing in System on Chip (SoC) devices. To keep on with this demand, manufacturers rely on embedded Flash memories that are easily scalable and relatively cheap to manufacture. These memories usually take a large percentage of the die area, and their reliability and verification process are thus two of the critical factors for a high yield. The testing efforts ensure that each commercialized device is compliant with the provided specifications but has to deal with a set of faults specific to embedded flash memories. Tests must span from pure analogic power measurements to individual cell-by-cell functionality checks. For the latter, Built In Self Test (BIST) is the most efficient solution given its orders of magnitude reduction in test time (compared to CPU-controlled tests), with a minimal cost due to the increased circuit complexity and die area. Given the regular structure of flash memories, BISTs are easily implemented and replicated multiple times. Such testing solutions allow the verification of all the banks in parallel, further increasing the advantages of the BIST. Carefully organizing both hardware and software components of the BISTs may lead to a significant reduction in test time without affecting the final test quality. Looking at it from another perspective, the BISTs may generate a considerable amount of diagnostic data during the tests. Efficiently collecting this data is crucial for designers and test engineers who can improve the production process or strengthen their design. An intelligent solution for this task is an on-chip method to compact diagnostic information during embedded memory testing. This strategy permits the reconstruction of failure bitmaps without any loss. The proposed method uses a fraction of the memory requested by a coordinatebased bit mapping approach. At the cost of a moderate test time overhead, this strategy permits dramatically increasing the number of devices that can be fully dia

Evaluating Burn-In related Metrics for large Automotive Systems-on-Chip. Francesco ANGIONE1, Paolo BERNARDI1, Andrea CALABRESE1, Stefano QUER1, Davide APELLO2, Vincenzo TANCORRE2, Roberto UGIOLI2 1Politecnico di Torino, Italy, 2STMicroelectronics, Italy, MBSA Approaches Applied to Next Decade Digital Components. Tiziano FIORUCCI1, Jean-Marc DAVEAU1, Emmanuel ARBARETIER2, GIORGIO DI NATALE3, Thomas JACQUET2 1STMicroelectronics, Crolles, Frances, 2APSYS-AIRBUS, France, 3Univ. Grenoble Alpes/CNRS/TIMA, France, Monitoring and controlling handler temperature. Guy DECABOOTER Onsemi, Belgium

Hardware obfuscation or logic locking (LL), relate to a method of safeguarding hardware intellectual property (IP) blocks against a variety of attacks, such as, IP theft, reverse engineering, and malicious alterations. Modern locking strategies primarily focus on preventing illegal use of a design by limiting correct functionality; they rarely address preventing extraction of design secrets through structural analysis. The locking gates are also vulnerable to removal attempts due to a lack of structural obfuscation. In this work, we analyze the structural alterations caused by LL and introduce a new class of attacks (SAIL, SURF) and associated CAD platform that take advantage of these artifacts. SAIL can expose the structural vulnerabilities of a locked design through a systematic set of steps and open it up for subsequent key-retrieval/reverse-engineering attacks. SAIL is far stronger than prevalent attacks such as SAT-based attacks because SAIL does not require an unlocked-IC or golden I/O responses to carry out the attack. We have also proposed the SIVA-Metric which can be used to quantify the existing structural vulnerabilities of a given design. It can be directly computed without additional training requirements. The SURF attack leverages the structural analysis output of SAIL to mount a subsequent key-retrieval attack. Through extensive quantitative analysis, we have demonstrated the efficacy of the proposed attacks/metrics.

The work presented here is on back-annotation of physical properties into components of an embedded system for system-level simulation and facilitating fast design space exploration. Two important properties, power and noise are considered in this thesis. A general ML-based framework is proposed for both power and noise back-annotation. This framework removes the expensive low-level simulations and performs a one-time offline effort for low-level property characterization. The actual data from characterization generates the dataset for training ML-based models. We evaluate several ML techniques on this task like multi-layer perceptron, convolutional neural network, gradient boosting, and LSTM. The trained model will be implemented in a fast SystemC surrogate model that speeds up the simulation time for system design space exploration. In this paper the methodology will be explained for interconnect crosstalk back-annotation. A crosstalk model for a RISC-V like processor interconnects is implemented and evaluated as a case study. The same methodology is used for backannotating and evaluating processor power at system level.

With the rapid growth of IoT and embedded devices, the development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Resistive Random Access Memory (ReRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Intrinsic properties of ReRAMs make them suitable for the implementation of basic security primitives such as Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs). The studies to be carried out during this thesis will allow the creation of robust, low cost and reliable security primitives by exploiting the inner variability of memristive technologies.

Embedded nano-electronic systems are becoming more prevalent in people’s daily lives. As a result, chip and embedded system manufacturing has become increasingly complicated and huge in recent years. Therefore, anomalous system behaviors also continue to be more increasingly present. Thinking about safety-critical sectors, such as automotive, aerospace, or medical, it is evident how managing system anomalies and defects become vital; in fact, an overlooked defect could lead to dangerous scenarios for human lives. Therefore, there must be a set of rigorous control techniques in all phases prior to the commercialization of a system (testing techniques). Moreover, impressive processing capabilities are integrated on a single chip in today’s environment. As a result, manufacturers are faced with significant complexity in testing their embedded systems. They became so huge in terms of the number of transistors composing them and complex that the old methods and techniques cannot manage and test them anymore, especially in terms of time. For this reason, it is necessary to develop and investigate innovative methodologies that can guarantee high reliability despite the complexity of modern Systems-on-Chip in safety critical fields.

Strategies for Enabling Quantum Development with Test and Measurement at millikelvin range focusing on pre-characterization. Jack DEGRAVE1, Philip KRANTZ2, Dong-Thuc KNOBBE1 1FormFactor, USA, 2Keysight, USA, Challenges and Solutions for Automotive Cold Test Elimination. Chen HE NXP Semiconductors, USA, RETE: DfRT, Test for Reliability & Data Analysis for zero defects and zero scraps. Mauro PIPPONZI, Alessandro MASERI, Luca MORICONI ELES Semiconductor Equipment, Italy, 3D interconnect Test Challenge. Sreejit CHAKRAVARTY Intel, USA

It is well known that during device testing, the switching activity (SWA) of the circuit under test (CUT) is an important parameter that must be retained to a minimal value in order to avoid unwanted scenarios on the CUTs (e.g., over-stressing) that can lead to an artificial yield loss. However, there are scenarios, e.g., during Burn-In testing (BI), where the maximization of the SWA can be proven beneficial by accelerating the aging phenomena of the devices in a safer and better controlled manner. In the frame of my PhD activities, I look for new methods able to automatically generate programs able to maximize the switching activity in a SoC and/or in the single modules within it. I already developed two methods while considering microprocessors as case studies, that automate the generation of stress-inducing stimuli for various units of a pipelined CPU. The first method is based on evolutionary techniques, while the second is based on formal techniques. The microprocessor we considered is the OpenRISC 1200 (OR1200).