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This paper presents a scalable, fully-unrolled Number Theory Transform (NTT) architecture that eliminates memory registers. This architecture leverages Dual-Mode Logic (DML) technology to achieve configurability for various input sizes $(N)$ and bit-widths $(K)$ . The design targets hardware acceleration, aiming to deliver NTT functionality at the speed of signal propagation without relying on registers or incurring pipeline-related trade-offs. Our implementation offers several potential optimizations, including a unique, fully-combinational, and low-cost modular reduction technique within the K-RED algorithm. Furthermore, it eliminates memory access penalties and control overhead. The widespread adoption of NTT and similar repeated structures across various fields underscores the broad applicability of our findings. Similar to large-scale DML-based architectures (e.g., MAC multipliers), our DML-NTT design can optimize both performance and energy consumption compared to standard CMOS implementations. Evaluation against its CMOS counterpart and a diverse set of existing hardware NTT implementations demonstrates high efficiency. For instance, an NTT with $N = 2^{10}$ and $K = 2^{5}$ bits achieves either high energy efficiency ( $0.227~\mu $ J in static mode) or superior performance ( $0.018~\mu $ s in dynamic mode). These results surpass all known synchronous/iterative (rolled) or memory-based designs to date. Compared to an unrolled CMOS implementation, our design offers a 2x performance improvement in dynamic mode, albeit at a 5x energy cost. Additionally, the design incorporates a static mode that exhibits performance nearly identical to the unrolled CMOS architecture, providing flexibility for design considerations.

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approach offers maximum PDP reduction of 33.52%, 99.39% and 96.61% for 2-input gates as compared to their footed DML, DMPL and DMTGDI counterparts, respectively. The reduction in PDP is quite significant in 1-bit full adder circuit where the corresponding values are 94.18%, 99.41% and 99.79%, respectively. [ABSTRACT FROM AUTHOR]

This paper puts forward a proposal to reduce leakage power in dual mode logic (DML) circuits by adapting LECTOR (LEakage Control TransistOR) technique and the circuits so obtained are referred to as L-DML circuits. The concept is elucidated through footed Type A and Type B DML based gates which are called LDML-TA and LDML-TB. The leakage power for two and four input NAND and NOR gates implemented through DML and LDML circuits is measured in static and dynamic mode through simulative investigations at 90 nm and 45 nm nodes using the Symica DE tool. The performance of the proposal is investigated using standard and high threshold transistor variants in LECTOR technique. The dependence of leakage power on temperature is also studied for both DML and LDML circuits. It is observed that the leakage power of the circuits exhibits an upward trend with lowering of technology node and increase in temperature irrespective of the mode of operation. In static mode, the maximum power saving for LDML-TA is 58.9% at 27 °C whereas the corresponding saving in LDML-TB is 66.6% for 2-input design. Similarly, the LDML-TA and LDML-TB show power saving of (28.5%, 58.9%) and (32.5%, 66.6%) in (pre-charge, evaluate) states respectively in dynamic mode. [ABSTRACT FROM AUTHOR]

A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.

Abstract In this paper, a double-precision carry-save adder (CSA)-based array multiplier is designed using the Dual Mode Logic (DML) approach in a commercial 65-nm low-power CMOS technology. DML typically allows on-the-fly controllable switching at the gate level between static and dynamic operation modes. The proposed multiplier exploits this unique ability of DML to efficiently trade performance and energy consumption when considering on-demand double-precision (8 × 8-bit or 16 × 16-bit) operations. This occurs in the DML multiplier working in a mixed operation mode, i.e., by employing the static and dynamic mode for lower and higher precision operations, respectively. In fact, the use of the dynamic mode for higher precision operations ensures higher performance as compared to the standard CMOS circuit (16% gain on average) at the cost of higher energy consumption. Such energy penalty is counterbalanced at lower precision operations where the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard CMOS implementation and to the case when using either the static or the dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, our DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations. Highlights • A double-precision (8 × 8-bit or 16 × 16-bit) multiplier is designed using the Dual Mode Logic (DML) in a 65-nm CMOS technology. • This multiplier works in a mixed operation mode by switching between static and dynamic mode according to the different precision. • Such mixed mode allows boosting the gain in energy-delay product (EDP) of the DML circuit with respect to its CMOS counterpart. • When compared to the CMOS circuit, our DML design working in the mixed mode exhibits an average gain of 15% in terms of EDP. • Such benefit is maintained over a wide range of process-voltage-temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to improve energy efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the design's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption reduction. The proposed approach is analyzed on a 128 bit carry skip adder. Simulations, carried out in a standard 40 nm digital CMOS process with , show that the proposed approach allows performance improvement of X2 along with reduction of energy consumption of X2.5, as compared with a standard CMOS implementation. At , improvements of 1.3X and 1.5X in performance and energy are achieved, respectively.

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder. [ABSTRACT FROM AUTHOR]

In recent years, the major focus of VLSI design has shifted from high-speed to low-power consumption. While standard CMOS-based digital design provides substantial flexibility during pre-silicon design phases, the characteristics of the gates are set by fabrication variations and environmental conditions and cannot easily be changed at runtime. The recently proposed Dual Mode Logic (DML) family provides a novel approach to provide this capability by introducing two configurable operating modes, static and dynamic, that enable fine-grained control of the power-performance tradeoff of a logic path. However, the introduction of a new topology requires the development of both a design methodology and techniques for integration in a robust design automation flow. Standard synthesis tools do not support dynamic gates, and in particular, dual-characteristic gates. Therefore, until now, DML has been limited to small, custom-made blocks and components. In this paper, we present a novel approach for the integration of DML into standard electronic design automation tools, as part of the standard digital design flow. The development of this approach and the accompanying design methodology enables DML to be used in larger designs, such as state-of-the-art, high-speed and/or low-power SoCs. We demonstrate the employment of the proposed approach in order to benefit from DML properties, and reduce the power consumption, while simultaneously improving the operating frequency of a number of test designs. [ABSTRACT FROM AUTHOR]

Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process. [ABSTRACT FROM AUTHOR]

Abstract: The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40nm DML basic gates. The design example of a DML full adder, implemented in a 40nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations. [Copyright &y& Elsevier]

This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving. [ABSTRACT FROM AUTHOR]

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. [ABSTRACT FROM AUTHOR]