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Abstract: A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100MHz switching frequency are presented to validate the proposed methodology. [Copyright &y& Elsevier]

Solar cell equivalent circuit modelling is usually based on continuous I-V models, with a set of data obtained by analytical expressions. This work proposes an almost discrete novel mathematical method and correspondent electrical model, based on the I-V curve adjustment at every two adjacent points. It is based on the discretisation of any diode model behaviour, such as the 1M5P (also known as 1D5P) or the 1M7P (also known as 2D7P). For this reason, the model is named d1MxP, meaning that it is a discrete (d) model (1M) with x parameters (xP). The modelling methodology validation process uses experimental data already published in the literature. According to the presented results, the proposed method shows increased accuracy when compared to the 1M5P or 1M7P equivalent models. The accuracy on the maximum power point and fill factor determination is relevant, resulting in an improvement of up to 3.34% in the maximum power, up to 5.70% in its voltage and up to 8.20% in its current, for the analysed data. Furthermore, Fill Factor values, have variation from up to 35.98%. The temperature influence on the silicon solar cell is also analysed, to validate the results. The proposed method allows highly accurate curve fitting to the (experimental) points and consequently, to obtain a more accurate model to analyse the performance of solar cells under different conditions. [ABSTRACT FROM AUTHOR]

This paper describes an energy harvesting system composed of an organic photovoltaic cell (OPV) connected to a DC–DC converter, designed in a 130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, with a quasi- maximum power point tracking (MPPT) algorithm to maximize the system efficiency, for indoor applications. OPVs are an emerging technology with potential for low cost indoor light energy harvesting. The OPV current-voltage curves (I-V) under an irradiance of solar simulator Oriel Sol 3A, at room temperature, are obtained and an accurate electrical model is derived. The energy harvesting system is subjected to four different indoor light sources: 35 W halogen, 3.5 W LED, 5 W LED, and 7 W LED, positioned at three different heights (0.45 m, 0.26 m, and 0.11 m), to evaluate the potential of the system for indoor applications. The measurements showed maximum efficiencies of 60% for 35 W halogen and 45% for 7 W LED at the highest distance (0.45 m) and between 60% (5 W LED) and 70% (35 W halogen), at the shorter distance (0.11 m). Under irradiation, the integrated CMOS circuit presented a maximum efficiency of 75.76%, which is, to the best of the authors' knowledge, the best reported power management unit (PMU) energy system using organic photovoltaic cells. [ABSTRACT FROM AUTHOR]