Search

The low-frequency noise (LFN) in downscaled silicon transistors has become prominently large, and it occurs as a limiting factor for diverse applications. Considerable interest is paid to the “slow” (as compared to the operating frequency of the devices) noise. Therefore, we address the trends for LFN from an extensive analysis of data from many publications over a very long period. The impact of LFN on high-frequency device performance, the penalties associated with using composite materials, and unsolved issues are also discussed. [ABSTRACT FROM AUTHOR]

By the continuing downscaling of sub-micron transistors in the range of few to sub-decananometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10 nm × 10 nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial "frozen noise", which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the "frozen noise" contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of "innovation variance", which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the "statistics behind the numbers", because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law. [ABSTRACT FROM AUTHOR]

An n+ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this article. The merged impact of both lateral and vertical tunneling due to n+ pocket in the gate–source overlap region enhances the ON current and provides steeper subthreshold swing (SS). The dielectric pocket at channel drain junction depletes the drain region at channel drain interface. Consequently, the minimum tunneling width at channel drain interface is enhanced to offer significant suppression of ambipolar conduction in a TFET. The proposed TFET structure offers a high ON/OFF current ratio of 1.57 × 1010 and considerably low SS of 8 mV/dec along with reduced ambipolar conduction up to a larger negative bias region. The impact of parametric variation of the proposed structure is studied and optimized accordingly. Noise characteristics of the proposed SOI TFET are investigated to realize the reliability issues of the device. Besides, the impact of elevated temperature on transfer characteristic and various RF parameters including transconductance (gm), total gate capacitance (Cgg), gate to drain capacitance (Cgd), cutoff frequency (ft), gain bandwidth product (GBP) and intrinsic delay (τ), respectively, have been investigated. The device performance has been upgraded by the rise in cutoff frequency and drop in intrinsic delay at high temperature. [ABSTRACT FROM AUTHOR]

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-μm three-dimensional (3-D)—SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D—SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D—SOI technology are also characterized and compared with conventional bulk CMOS technology. [ABSTRACT FROM AUTHOR]

The performance of monolithically integrated metal-semiconductor-metal/high electron-mobility transistor (MSM/HEMT) and p-i-n/HEMT photoreceivers is reported. p-i-n/HEMT photoreceivers have been designed and fabricated, resulting in measured transimpedances of 700 Ω, an 8.3-GHz bandwidth, and measured sensitivities of -17.7 dBm at 10 Gb/s and -15.8 dBm at 12 Gb/s for a 231 - 1 pattern length pseudorandom bit sequence at a bit error rate of 10-9. Low-noise MSM-based pbotoreceivers have also been designed and fabricated, and frequency response, noise, and sensitivity measurements have been performed. Sensitivities of -16.9, -13.1, and -10.7 dBm were obtained at 5, 8, and 10 Gb/s, respectively. A direct comparison of p-i-n- and MSM-based photoreceivers is undertaken on photoreceivers with matched responsivity and bandwidth. Measurement and theoretical analysis of circuit and device noise indicates an anomalous sensitivity penalty in MSM-based receivers that arises due to intersymbol interference [ABSTRACT FROM PUBLISHER]

The noise characteristics of a monolithically integrated pin-FET were analyzed using the circuit simulator SPICE This device consists of InGaAs p-i-n photodiodes (PDs) and InGaAs-channel junction field-effect transistors (JFETs). The equation for the metal-semiconductor field- effect transistor (MESFET) model of the SPICE simulator is modified to fit the noise characteristics of the fabricated InGaAs channel WETs. Then the noise parameters are extracted by fitting the simulation results to the measured noise characteristics of the pin-FET. The sensitivity degradation caused by the noise from the two noise sources in the monolithic pin-FETs is analyzed by circuit simulations using these noise parameters. The noise sources considered in this analysis are the load FET at the common-source amplifier stage and the level-shift diodes introduced to provide the operation with a single power supply. Finally, the measured sensitivity differences among the channels of the fabricated four-channel pin-FET any are analyzed and it is shown that they agree with the simulation results when the flicker noise is proportional to 1/f0.8 where f is the frequency. This simulation technology is useful for analyzing the noise factors that dominate the noise characteristics and can be used to predict the sensitivity when designing monolithic photo- receivers. [ABSTRACT FROM AUTHOR]