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In this study, we propose a dual-stream UNet neural network architecture design named CPF-UNet, specifically designed for efficient semantic pixel-level segmentation tasks. This architecture cleverly extends the basic structure of the original UNet, mainly through the addition of a unique attention-guided branch in the encoder part, aiming to enhance the model’s ability to comprehensively capture and deeply fuse contextual information. The uniqueness of CPF-UNet lies in its dual-path mechanism, which differs from the dense connectivity strategy adopted in networks such as UNet++. The dual-path structure in this study can effectively integrate deep and shallow features without relying excessively on dense connections, achieving a balanced processing of image details and overall semantic information. Experiments have shown that CPF-UNet not only slightly surpasses the segmentation accuracy of UNet++, but also significantly reduces the number of model parameters, thereby improving inference efficiency. We conducted a detailed comparative analysis, evaluating the performance of CPF-UNet against existing UNet++ and other corresponding methods on the same benchmark. The results indicate that CPF-UNet achieves a more ideal balance between accuracy and parameter quantity, two key performance indicators.

Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method-at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively. [ABSTRACT FROM AUTHOR]

Copyright of GeSec: Revista de Gestao e Secretariado is the property of Sindicato das Secretarias e Secretarios do Estado de Sao Paulo (SINSESP) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The decoder is an integral part of modern memory, processors. In this work, a 5 to 32 and 6 to 64 decoders have been designed and characterized using low-order decoders for the state-of-the-art digital systems. The Design and Synthesis work have been executed at the Register Transfer Level (RTL) and the Testbench based Verification has been performed to ensure the functional correctness of the designs with timing constraints. RTL Coding is done at VerilogHDL Std. IEEE 1364-2001 and IEEE 1364-2005. It is observed that the 5 to 32 and 6 to 64 order decoders utilize the highest 15% and 30% bonded IOBs where the 2 to 4 decode 2% only. It is found that the 6 to 64 decoders have 5% higher delay to 5 to 32 decoders whereas the 5 to 32 decoder has 5.5% more logic delay and 9.1% less route delay as compared to the 6 to 64 decoders. [ABSTRACT FROM AUTHOR]

Multipliers are the most demanding component of any filter. They not only dominate most of the chip area but also contribute to most of the computational delay. An efficient realization of filter thus requires optimization of the multipliers. In this paper, a high performance block reconfigurable finite impulse response filter structure is presented. Block-based realization improves the overall throughput of the structure. A novel partial-product-based structure is proposed for Multiply and Accumulation operation, instead of traditional multipliers-based structure. Pipelining and parallelism in the structure improves the throughput of the design. The reuse of the partial products reduces the number of adders and increases the speed, thereby reducing the area-delay product (ADP) and energy-per output (EPO), in comparison with the earlier reported structures. The comparative analysis is done with the help of ASIC synthesis results and the results show that the proposed architecture for filter order 16 and block input 8requires 28.91% less ADP and 25.72% less EPO than the earlier reported architecture. [ABSTRACT FROM AUTHOR]

Many machine vision applications, such as semantic segmentation and depth prediction, require predictions for every pixel of the input image. Models for such problems usually consist of encoders which decrease spatial resolution while learning a high-dimensional representation, followed by decoders who recover the original input resolution and result in low-dimensional predictions. While encoders have been studied rigorously, relatively few studies address the decoder side. This paper presents an extensive comparison of a variety of decoders for a variety of pixel-wise tasks ranging from classification, regression to synthesis. Our contributions are: (1) decoders matter: we observe significant variance in results between different types of decoders on various problems. (2) We introduce new residual-like connections for decoders. (3) We introduce a novel decoder: bilinear additive upsampling. (4) We explore prediction artifacts. [ABSTRACT FROM AUTHOR]

In order to explore the gaps between decoder's interpretations and encoder's designing intentions with respect to the same multimodal discourses, thirty linguistic and thirty art graphic participants were chosen as decoders and encoders, respectively. The participants were required to interpret the same research data in terms of the best and the worst major colors, as well as the best and the worst synergetic patterns formed by major modes. It was found that the complete unanimity in terms of both color and spatial arrangements among the interpretations between participants only reached 43.3%. The unanimity in the interpretations from the perspective of color alone reached 46.7%. Moreover, the interpretations from the perspective of spatial arrangements present high unanimity, with a rate up to 70%. It is concluded that there are both differences and similarities between the interpretations made by encoders and decoders. The possible reasons underlying both differences and similarities are probed in the present study as well. [ABSTRACT FROM AUTHOR]

Active error decoding and correction of topological quantum codes--in particular the toric code-- remains one of the most viable routes to large scale quantum information processing. In contrast, passive error correction relies on the natural physical dynamics of a system to protect encoded quantum information. However, the search is ongoing for a completely satisfactory passive scheme applicable to locally interacting two-dimensional systems. Here, we investigate dynamical decoders that provide passive error correction by embedding the decoding process into local dynamics. We propose a specific discrete time cellular-automaton decoder in the fault tolerant setting and provide numerical evidence showing that the logical qubit has a survival time extended by several orders of magnitude over that of a bare unencoded qubit. We stress that (asynchronous) dynamical decoding gives rise to a Markovian dissipative process. We hence equate cellular-automaton decoding to a fully dissipative topological quantum memory, which removes errors continuously. In this sense, uncontrolled and unwanted local noise can be corrected for by a controlled local dissipative process. Weanalyze the required resources, commenting on additional polylogarithmic factors beyond those incurred by an ideal constant resource dynamical decoder. [ABSTRACT FROM AUTHOR]

Active error decoding and correction of topological quantum codes—in particular the toric code—remains one of the most viable routes to large scale quantum information processing. In contrast, passive error correction relies on the natural physical dynamics of a system to protect encoded quantum information. However, the search is ongoing for a completely satisfactory passive scheme applicable to locally interacting two-dimensional systems. Here, we investigate dynamical decoders that provide passive error correction by embedding the decoding process into local dynamics. We propose a specific discrete time cellular-automaton decoder in the fault tolerant setting and provide numerical evidence showing that the logical qubit has a survival time extended by several orders of magnitude over that of a bare unencoded qubit. We stress that (asynchronous) dynamical decoding gives rise to a Markovian dissipative process. We hence equate cellular-automaton decoding to a fully dissipative topological quantum memory, which removes errors continuously. In this sense, uncontrolled and unwanted local noise can be corrected for by a controlled local dissipative process. We analyze the required resources, commenting on additional polylogarithmic factors beyond those incurred by an ideal constant resource dynamical decoder.

We address the problem of universal decoding in unknown frequency-selective fading channels, using an orthogonal frequency-division multiplexing (OFDM) signaling scheme. A block-fading model is adopted, where the bands' fading coefficients are unknown yet assumed constant throughout the block. Given a codebook, we seek a decoder independent of the channel parameters whose worst case performance relative to a maximum-likelihood (ML) decoder that knows the channel is optimal. Specifically, the decoder is selected from a family of quadratic decoders, and the optimal decoder is referred to as a quadratic minimax (QMM) decoder for that family. As the QMM decoder is generally difficult to find, a suboptimal QMM decoder is derived instead. Despite its suboptimality, the proposed decoder is shown to outperform the generalized likelihood ratio test (GLRT), which is commonly used when the channel is unknown, while maintaining a comparable complexity. The QMM decoder is also derived for the practical case where the fading coefficients are not entirely independent but rather satisfy some general constraints. Simulations verify the superiority of the proposed QMM decoder over the GLRT and over the practically used training sequence approach. Index Terms--Decoding, fading channels, generalized likelihood ratio test (GLRT), maximum-likelihood (ML) decoding, minimax methods, orthogonal frequency-division multiplexing (OFDM), quadratic minimax (QMM) decoders, universal decoding.

The single-event upset (SEU) rate in a flash analog-to-digital converter (ADC) AD9058 on board a space experiment varied by more than an order of magnitude, depending on the input. A pulsed laser aided in elucidating the reasons, which were found to be the result of the unique design of the AD9058. Index Terms--Analog-to-digital converter (ADC), decoding security, single-event upsets (SEUs), space radiation.

We show that for the case of the binary-symmetric channel and Gallager's decoding algorithm A the threshold can, in many cases, be determined analytically. More precisely, we show that the threshold is always upper-bounded by the minimum of 1-[[lambda].sub.2] [rho]' (1)/[lambda]'(1) [rho]' (1) - [[lambda].sub.2][rho]' (1) and the smallest positive real root [TAU] of a specific polynomial p(x) and we observe that for most cases this bound is tight, i.e., it determines the threshold exactly. We also present optimal degree distributions for a large range of rates. In the case of rate one-half codes, for example, the threshold [x.sup.*.sub.0] of the optimal degree distribution is given by [x.sup.*.sub.0] ~ 0.0513663. Finally, we outline how thresholds of more complicated decoders might be determined analytically. Index Terms--Analysis, degree distribution, low-density parity-check (LDPC) codes, optimal, threshold, turbo code.

A number of different iterative decoding methods are proposed for the multiuser interference cancelation in a code-division multiple-access system where turbo-codes are utilized for forward error correction (FEC). In the proposed methods, the individual users are decoded separately with the operation of iterative interference cancelation being mixed with the iterative decoding of turbo-code. This results in a modest increase in the overall complexity as compared to a conventional single-user receiver utilizing turbo-code for FEC. Numerical results are presented showing that the proposed iterative decoders show an improvement in the bit error rate performance and/or a reduction in the computational complexity as compared to similar previously known methods reported in [2] and [3]. Index Terms--Code-division multiple access (CDMA), iterative decoding, multiunder interference cancellation.

In this correspondence, we consider turbo decoding of parallel concatenated single parity check (SPC) (K + 1, K) codes, with row-column interleaving. Existence and uniqueness of the asymptotic probability density evaluated with the turbo algorithm is proved for every length K and every signal-to-noise ratio (SNR). Index Terms--Iterative decoding, product codes, single parity check (SPC) codes, turbo algorithm.

This paper presents a low-power variable length decoder exploiting the statistics of successive codewords. The decoder employs small look-up tables working as fixed caches to reduce the number of activations of a variable length code detector where considerable power is consumed. The power simulation results estimated using PowerMill show that 35% energy is reduced on the average compared to the previous low-power scheme. Index Terms--Huffman, low power, MPEG-2, variable length code, variable length decoder.

This paper presents mathematical derivations for a type of maximum-likelihood sequence detector (MLSD), for decoding signals equalized to the ternary partial response fundamental polynomials--duobinary (1 + D) and dicode (1 - D); or part of decoders for higher-order class of partial response polynomials. Region-dependent but algorithmically directed thresholds with relatively simple updates for ternary duobinary (1 + D) and dicode (1 - D) channel decoders are hereby presented which depend only on state metric differences. The simplicity of the threshold updates makes the new proposition very attractive for hardware implementation. Derivations for a ternary duobinary and dicode partial-response signaling (PRS) channel decoder based on the true difference metric algorithm are included. Index Terms--Analog decoders, partial-response signaling (PRS), Viterbi algorithm.

In this paper, a set of variables which can be easily computed in the course of iterative decoding of turbo decoders named turbo decoding metrics (TDMs) are introduced. TDMs are measured twice per iteration. According to the measured values, a lot of information other than the signal-to-noise ratio (SNR) in the received data, such as how good (or bad) the current decoding block is and how close to the convergence the current decoding is, can be obtained. Detailed discussions are provided regarding why these variables are considered. Based on the measured TDMs after the first iteration, an approximate channel reliability value (denoted as [L.sub.c]) can be obtained for MAP-based turbo decoders. Simulation results show that there is no performance degradation if approximated [L.sub.c] values are used instead of using exact values. It is also shown that the adaptive decoding approach employing TDMs is more efficient than all existing methods in terms of hardware and latency. Other applications of TDMs are also pointed out. Index Terms--Adaptive decoding, blind decoding, decoding metrics, error correction code, statistical property, turbo code.

Copyright of Estudios Penales y Criminológicos is the property of Universidad de Santiago de Compostela, Servicio de Publicaciones and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents two novel genetic algorithms (GAs) for hard industrially relevant packing problems. The design of both algorithms is inspired by aspects of molecular genetics, in particular, the modular exon-intron structure of eukaryotic genes. Two representative packing problems are used to test the utility of the proposed approach: the bin packing problem (BPP) and the multiple knapsack problem (MKP). The algorithm for the BPP, the exon shuffling GA (ESGA), is a steady-state GA with a sophisticated crossover operator that makes maximum use of the principle of natural selection to evolve feasible solutions with no explicit verification of constraint violations. The second algorithm, the Exonic GA (ExGA), implements an RNA inspired adaptive repair function necessary for the highly constrained MKP. Three different variants of this algorithm are presented and compared, which evolve a partial ordering of items using a segmented encoding that is utilised in the repair of infeasible solutions. All algorithms are tested on a range of benchmark problems, and the results indicate a very high degree of accuracy and reliability compared to other approaches in the literature. [ABSTRACT FROM AUTHOR]

Super-orthogonal space-time trellis codes (SOSTTCs) designed by hand can significantly improve the performance of space-time trellis codes. This paper introduces a new representation of SOSTTCs based on a generator matrix that allows a systematic and exhaustive search of all possible codes. This will verify that some of the known codes are optimal, and provides a means to easily implement encoders and decoders with a large number of states without relying on a graphical representation. New codes with up to 256 states that outperform previously known codes are presented [ABSTRACT FROM PUBLISHER]

This paper demonstrates a high-performance optical-code-division-multiple-access (O-CDMA) network testbed using the spectral phase encoded time spreading (SPECTS) method. Through additional time and polarization multiplexing, a total of 32 10-Gb/s users are supported while sharing eight O-CDMA spreading codes. User detection is achieved with time gating and nonlinear thresholding to suppress the multiaccess interference of other users. Incorporation of forward error correction successfully reduces the performance loss imposed by coherent beat interference, resulting in error-free performance (BER<10-11), significant per-user power penalty reduction, and the elimination of a bit-error-rate noise floor. The testbed also applies bandwidth suppression within the encoders and decoders, yielding a 52% increase in spectral efficiency [ABSTRACT FROM PUBLISHER]

In this letter, we derive analytical expressions for the bit error rate (BER) of space-time block codes (STBC) from complex orthogonal designs (COD) using quadrature amplitude modulation (QAM) on Rayleigh fading channels. We take a bit log-likelihood ratio (LLR) based approach to derive the BER expressions. The approach presented here can be used in the BER analysis of any STBC from COD with linear processing for any value of M in an M-QAM system. Here, we present the BER analysis and results for a 16-QAM system with i) (2-Tx, L-Rx) antennas using Alamouti code (rate-1 STBC), ii) (3-Tx, L-Rx) antennas using a rate-1/2 STBC, and iii) (5-Tx, L-Rx) antennas using a rate-7/11 STBC. In addition to being used in the BER analysis, the LLRs derived can also be used as soft inputs to decoders for various coded QAM schemes, including turbo coded QAM with space-time coding as in high speed downlink packet access (HSDPA) in 3G. [ABSTRACT FROM PUBLISHER]

Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048×2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 1011 b/cm2. [ABSTRACT FROM PUBLISHER]

This paper describes a study of the performance of various configurations for placing multiple optical amplifiers in a typical coherent ultrashort light pulse code-division multiple access (CULP-CDMA) communication system using the additive noise model. For this study, a comprehensive performance analysis was developed that takes into account multiple-access noise, noise due to optical amplifiers, and thermal noise using the saddle-point approximation technique. Prior to obtaining the overall system performance, the input/output statistical models for different elements of the system such as encoders/decoders, star coupler, and optical amplifiers were obtained. Performance comparisons between an ideal and lossless quantum-limited case and a typical CULP-CDMA with various losses exhibit more than 30 dB more power requirement to obtain the same bit-error rate (BER). Considering the saturation effect of optical amplifiers, this paper discusses an algorithm for amplifiers' gain setting in various stages of the network in order to overcome the nonlinear effects on signal modulation in optical amplifiers. Finally, using this algorithm, various configurations of multiple optical amplifiers in CULP-CDMA are discussed and the rules for the required optimum number of amplifiers are shown with their corresponding optimum locations to be implemented along the CULP-CDMA system. [ABSTRACT FROM PUBLISHER]

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent 5150 outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times Sd throughput for large blocks is increased up to six-fold relative to, sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area. [ABSTRACT FROM AUTHOR]

Low-density parity-check (LDPC) codes are excellent candidates for optical network applications due to their inherent low complexity of both encoders and decoders. A cyclic or quasi-cyclic form of finite geometry LDPC codes simplifies the encoding procedure. In addition, the complexity of an iterative decoder for such codes, namely the min-sum algorithm, is lower than the complexity of a turbo or Reed-Solomon decoder. In fact, simple hard-decoding algorithms such as the bit-flipping algorithm perform very well on codes from projective planes. In this paper, the authors consider LDPC codes from affine planes, projective planes, oval designs, and unitals. The bit-error-rate (BER) performance of these codes is significantly better than that of any other known foward-error correction techniques for optical communications. A coding gain of 9-10 dB at a BER of 10-9, depending on the code rate, demonstrated here is the best result reported so far. In order to assess the performance of the proposed coding schemes, a very realistic simulation model is used that takes into account in a natural way all major impairments in long-haul optical transmission such as amplified spontaneous emission noise, pulse distortion due to fiber nonlinearities, chromatic dispersion, crosstalk effects, and intersymbol interference. This approach gives a much better estimate of the code's performance than the commonly used additive white Gaussian noise channel model. [ABSTRACT FROM PUBLISHER]

A few years ago it was difficult for designers to differentiate themselves in graphics processing and video applications. Today, the situation has changed, thanks to several trends influencing the makers […]

Synchronization and image compression are the key IC technologies for putting video-in-a-window on PCs. Enthusiasm for PC multimedia has diminished but hasn't disappeared, and analysts are still touting the virtues […]

This paper extends a pulse propagation previously developed by Marcuse for the characterization of pulse transmission in single mode fibers to the case of pulsed optical code-division multiple-access (CDMA) systems that employ encoders and decoders based on ladder networks. The model accounts for important degradation factors such as fiber dispersion, source linewidth (coherence), chip time duration and phase and delay mismatch between the source encoder and the destination decoder. Although results are only presented for the autocorrelation signal, the model can be employed to analyze the impact of the above mentioned [ABSTRACT FROM PUBLISHER]