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The poster was presented at the Psi-k 2022 conference, August 22-25. The poster presetns the software development strategy and the current achievements of the European Centre of Excellence “Targeting Real chemical accuracy at the EXascale” (TREX). The main objective of TREX is the development of a user-friendly and open-source software suite in the domain of stochastic electronic structure simulations, which integrates a set of flagship quantum Monte Carlo codes within an interoperable, high-performance platform. Core of our software efforts is the creation of two libraries, the TREXIO and the quantum Monte Carlo kernel library (QMCkl).

TREX : an innovative view of HPC usage applied to Quantum Monte Carlo simulations The TREX[1] European Center of Excellence focuses on high accuracy quantum mechanical methods, essential in many different fields of application such as new material design or photochemistry. Among these methods, Quantum Monte Carlo (QMC) approaches are particularly well adapted to exascale architectures. Our ambition is to the help the community take advantage of exascale machines through the use of our HPC software. We will review in the presentation progress along the three following axes: * TREXIO[2]: A common I/O library and file format for easily exchanging data between applications, facilitating high-throughput computing workflows, * QMCkl[3]: A library of computational kernels specific to QMC applications written together by QMC and HPC experts, taking advantage of both CPUs and GPUs, * An integrated workflow including performance analysis (MAQAO[4]) and numerical accuracy measurements (Verificarlo[5]) to be used for the development of QMC kernels and more generally for improving the applications. In particular, we plan to identify the best performance usage of QMCkl and also to adjust the performance with numerical precision requirements. ------------------------------------ [1] https://trex-coe.eu [2] https://github.com/trex-coe/trexio [3] https://trex-coe.github.io/qmckl [4] https://www.maqao.org [5] https://github.com/verificarlo ------------------------------------ &nbsp

Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedded resource-constrained system, adapting stream programs to fit memory requirements is particularly important. In this paper we present a design-space exploration technique to reduce the minimal memory required when running stream programs on MPSoC; this allows to target memory constrained systems and in some cases obtain better performance. Using a set of semantically preserving transformations, we explore a large number of equivalent program variants; we select the variant that minimizes a buffer evaluation metric. To cope efficiently with large program instances we propose and evaluate an heuristic for this method. We demonstrate the interest of our method on a panel of ten significant benchmarks. As an illustration, we measure the minimal memory required using a multi-core modulo scheduling. Our approach lowers considerably the minimal memory required for seven of the ten benchmarks.

International audience; Characterizing performance is essential to optimize programs and architectures. The open source Adaptive Sampling Kit (ASK) measures the performance trade-off in large design spaces. Exhaustively sampling all sets of parameters is computationally intractable. Therefore, ASK concentrates exploration in the most irregular regions of the design space through multiple adaptive sampling strategies. The paper presents the ASK architecture and a set of adaptive sampling strategies, including a new approach called Hierarchical Variance Sampling. ASK's usage is demonstrated on three performance characterization problems: memory stride accesses, Jacobian stencil code, and an industrial seismic application using 3D stencils. ASK builds accurate models of performance with a small number of measures. It considerably reduces the cost of performance exploration. For instance, the Jacobian stencil code design space, which has more than 31 × 10^8 combinations of parameters, is accurately predicted using only 1500 combinations.

International audience; Current architecture complexity requires fine tuning of compiler and runtime parameters to achieve best performance.Autotuning substantially improves default parameters in many scenarios but it is a costly process requiring long iterative evaluations. We propose an automatic piecewise autotuner based on CERE (Codelet Extractor and REplayer). CERE decomposes applications into small pieces called codelets: each codelet maps to a loop or to an OpenMP parallel region and can be replayed as a standalone program.Codelet autotuning achieves better speedups at a lower tuning cost. By grouping codelet invocations with the same performance behavior, CERE reduces the number of loops or OpenMP regions to be evaluated. Moreover unlike whole-program tuning, CERE customizes the set of best parameters for each specific OpenMP region or loop. We demonstrate the CERE tuning of compiler optimizations, number of hreads,thread affinity, and scheduling policy on both NUMA and heterogeneous architectures. Over the NAS benchmarks, we achieve an average speedup of1.08x after tuning. Tuning a codelet is 13x cheaper than whole-program evaluation and predicts the tuning impact with a 94.7% accuracy. Similarly, exploring thread configurations and scheduling policies for a Black-Scholes solver on an heterogeneous big.LITTLE architecture is over 40x faster using CERE.