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CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 [micro]W (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption. Index Terms--Low-power transceivers, ultra-wide band (UWB), wireless body area networks (WBANs).

Ultra-wideband (UWB) impulse radios show strong advantages for the implementation of low-power transceivers. In this paper, we analyze the impact of CMOS technology scaling on power consumption of UWB impulse radios. It is shown that the power consumption of the synchronization constitutes a large portion of the total power in the receiver. A traditional technique to reduce the power consumption at the receiver is to operate the UWB radios with a very low duty cycle on an architecture with extreme parallelism. On the other hand, this requires more silicon area and this is limited by the leakage power consumption, which becomes more and more a problem in future CMOS technologies. The proposed quantitative framework allows systematic use of digital low-power design techniques in future UWB transceivers.