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This paper investigates the effects of the signal average power and the ambient temperature on the behavioral modeling and pre-distortion of high-power amplifiers concurrently. The measurement results showed that in addition to the signal average power, the behavior of a high-power PA is a function of ambient temperature as well. This paper proposes a novel smart Digital Pre-Distortion (DPD) model that considers both average Power and Temperature (PTI-DPD). The PTI-DPD is implemented using Artificial Intelligence (AI) based model and it benefits from sets of data formats containing the signal, its delayed versions, signal average power, and ambient temperature. The devised apparatus provides an uninterrupted linearization across the ambient temperature and signal average power span without need for any feedback or multiple models. A series of measurements have been conducted to study the PTI-DPD performance across the temperature and average power range. According to the results, the PTI-DPD achieves an average of -48.5 dBc Adjacent Channel Power Ratio (ACPR) across the average power and temperature span.

SamenvattingDe kosten van de gezondheidszorg stijgen. Bewustwording van daadwerkelijke kosten (in plaats van gemiddelde DBC-prijzen) is van groot belang om kosten te beteugelen. Hiertoe hebben wij voor 72 ureterorenoscopie (URS) procedures de gegevens over proceduretijd, materiaal, aanwezig personeel op OK, opname en follow-up prospectief geregistreerd. De totale kosten van een URS bedroegen gemiddeld € 2.819. De grootste kostenpost bestond uit chirurgische kosten (€ 2.075; 67,0%), gevolgd door opnamekosten (€ 514; 22,8%) en follow-upkosten (€ 230; 10,2%). Bij acht procedures bleek de steen gepasseerd ten tijde van de operatie en bleek de preoperatieve CT-scan ouder dan één maand. De kosten van deze procedures hadden voorkomen kunnen worden door een extra preoperatieve CT-scan te maken. Het verrichten van deze CT-scan zou een besparing kunnen opleveren van gemiddeld € 62 euro per procedure. De werkelijke kosten van een URS in dit cohort waren € 2.819, met als grootste kostenpost chirurgische kosten (€ 2.075). Het waarborgen van recente preoperatieve beeldvorming zou onnodige operaties en kosten kunnen besparen.

In the literature, giant magnetoresistive (GMR) point field detectors (PFDs) were integrated in terminals of Si IGBT modules for galvanically isolated current sensing in machine drives. This work presents a PFD-based current sensing system that can be fully integrated in the direct bonded copper (DBC) region of SiC power modules. The physics of phase shift errors caused by the Nickel (Ni) plating in the SiC power module is investigated. To address current sensing phase errors, a real-time phase shift reduction method is proposed. A bandwidth extension method is proposed to meet the sensing requirement of SiC devices that can switch at tens of kilohertz. The phase shift reduction and bandwidth extension methods are experimentally combined to sense the currents in the SiC DBC regions. The proposed current sensing has high bandwidth, minimal phase errors and low position sensitivity. The sensed currents can be used for high performance control and protection of SiC module-based converters.

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator's figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-E oscillator is implemented in a 0.18-μm CMOS technology. At 4 GHz, it exhibits a phase noise of -152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².

This brief presents a class-C voltage-controlled oscillator (VCO) that ensures a robust start-up with low phase noise and high power efficiency. The proposed start-up scheme, which uses a voltage converter that operates according to the output state, relieves the start-up difficulty by supplying a timevarying bias voltage to the core transistors and allows the VCO to operate in an optimal state. The start-up circuitry is enabled only during initial operation, so power efficiency is improved without phase noise degradation. Furthermore, a capacitor array with a high quality factor is implemented by a direct capacitor connection that exhibits low series resistance. Fabricated with a 65-nm CMOS, the VCO demonstrates a frequency tuning range of 13.1% from 19.3 to 22.0 GHz. The measured minimum phase noise at a 1-MHz offset is --106.33 dBc/Hz at an oscillation frequency of 19.7 GHz, while dissipating 3.8-mW of power from a 1.0-V supply. The VCO occupies an active area of 0.064 mm2. It reveals a figureof-merit and figure-of-merit with area of --186.4 and --198.3 dBc/Hz, respectively.

A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta-sigma modulation (DSM)-based randomization. Thus, a low spur level below -40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of -31.4/-42.7 and -28.2/-42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a 0.18 μm CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

We introduce a new mode of oscillation in an LC-tank: an inverse class-F₂₃. In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F₃) or/and to the second (in class-F₂/class-F₂₃) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves -95 dBc/Hz and -118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured 1/f³ corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM $_{T}$ ) of -196 and -199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

An under-sampling digital predistortion based on a multi-tone mixing feedback technique (MTM-DPD) is presented in this article. In contrast to the under-sampling digital predistortion (DPD) based on conventional receivers, the proposed method could simultaneously reduce the sampling rate and acquisition bandwidth using a multi-tone mixing (MTM)-based feedback channel. The MTM-DPD is implemented with an evolved direct learning architecture, where the coefficients of a predistorter are estimated based on the aliased feedback signal, preprocessed input signal, and preprocessed kernels of the DPD model. To preprocess the input signal and kernels, the behavioral model of the MTM-based feedback channel and its corresponding identification algorithm are analyzed in detailed. Experimental results show that for a gallium nitride (GaN)-based power amplifier (PA) with 40-MHz input, under the excitation of a 17 tone LO signal with frequency interval 7.68 MHz, the MTM-DPD with sampling rate 15.36 MSPS and acquisition bandwidth 15.36 MHz could improve the adjacent channel power ratio (ACPR) from -30.1 to -46.5 dBc and the error vector magnitude (EVM) from 9.13% to 1.76%. Compared with the conventional full sampling DPD (FS-DPD), the MTM-DPD could reduce the cost of analog-to-digital converters (ADCs) in feedback channel significantly while maintaining satisfactory linearization performance.

In this letter, a voltage-controlled oscillator (VCO) with low cost, wide-tuning range, and low phase noise is proposed based on substrate integrated suspended line (SISL) technology. Benefiting from the weak coupling between half-wavelength resonators, the Q value can be improved, so as to reduce the phase noise of the VCO. By introducing a varactor in the high-Q resonator, a wide-tuning range is achieved. All the used boards choose FR4 material with very low cost. The designed SISL VCO has a tuning range of 380 MHz and has a phase noise of -122.81 dBc/Hz at a 1-MHz offset relative to the 5.88-GHz carrier. Compared with the existing board-level VCOs, this design features a wide-tuning range and low phase noise based on a low-cost platform.

This letter presents a parallel-feedback dual-frequency oscillator (DFO) with low phase noise. It is achieved based on the filter switching technique. By using four switches to control two oscillator loops with a common active device, the oscillation frequency of the proposed DFO can be switched from one to another. Due to the high isolation level of the employed switches, the two oscillator loops almost operate independently. Thus, there is no intermodulation (IM) spurs generated in the output spectrum of the proposed DFO. In the meantime, to improve the phase noise performance of the DFO, each oscillator loop utilizes a high frequency-selectivity bandpass filter with high group delay (GD) as a frequency selective element. In this way, the low phase-noise DFO is developed. For demonstration, the DFO is designed, fabricated, and tested. As seen from the measurement results, the oscillator can oscillate at 2.04 or 3.092 GHz by controlling the four switches. At 100 kHz and 1 MHz frequency offset from the carrier frequency, the phase noises are -108.5 and -129.7 dBc/Hz for 2.04 GHz, while -112.7 and -135.7 dBc/Hz for 3.092 GHz.

In this article, a novel design method of dual-band and dual-state (DBDS) Doherty power amplifier (DPA) is proposed. Considering the actual parasitic parameters, the DPA can be designed by using the impedance transformation of saturation and back-off points at dual frequency bands of DBDS as well as second harmonic matching. The DBDS DPA for dual-band (DB) 5G application, i.e., 3.4 and 4.9 GHz band are designed and implemented, for the first time, by using metal-integrated and substrate-integrated suspended line (MI-SISL) technology, which has advantages of high performance and self-packaging. The fabricated DBDS DPA achieves the measured 44 and 43.2 dBm saturated power at 3.4 and 4.9 GHz bands, respectively. For the 3.4 and 4.9 GHz bands, the measured drain efficiency (DE) is 70.7% and 70.4% at peak power levels and 38% and 42% at a 6-dB output back-off, respectively. When driven by a 20- and 100-MHz modulated signal with 6-dB peak-to-average power ratio (PAPR), the adjacent channel leakage ratio is better than -27 dBc at operating frequencies. The average output power of 38 and 37 dBm with an average efficiency of 37.9% and 40.9% is achieved at 3.4 and 4.9 GHz, respectively.

Flexibility and tunability are critical for frequency conversion in antenna, radar and modern communication systems. In this study we propose and experimentally demonstrate a wideband tunable frequency converter by using an optoelectronic oscillator (OEO) to generate high-purity local oscillator (LO) signal for flexible frequency conversion. In the proposed frequency converter, a dual-polarization quadrature phase shift-keying (DP-QPSK) modulator is utilized to receive the signal to be converted and also to form a tunable OEO based on a dispersion-induced microwave photonic filter. By adjusting the bias voltage of the DP-QPSK modulator, an LO signal with accurate adjustable frequency is generated by the OEO. The measured phase noise of generated LO signal can reach -110 dBc/Hz at 10 kHz offset. An experiment is performed to verify the feasibility of this proposed frequency converter. The 7.6-GHz radio frequency (RF) signal is freely converted to different intermediate frequency (IF) signals, respectively. Moreover, the proposed microwave photonic converter is applied into wireless transmission systems. A 1-Gb/s NRZ wireless signal centered at 6.5 GHz is down-converted to baseband successfully.

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (QL) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on LgL-product simulation for a fixed Ibias. Employing the proposed resonator, a very low phase noise KUband VCO is designed and implemented in 0.18-lm CMOS technology. The measurement result shows that the proposed VCO has a phase noise of -110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of -191.95 dB.

This work proposes a new technique to reduce the phase noise (PN) and improve the tuning sensitivity of K-band voltage-controlled oscillators (VCOs) by increasing the quality (Q-) factor of the switched resonator. The proposed switched resonator consists of a high Q-factor half-circle inductor in parallel with an improved switched varactor and operates in four different frequency bands using a single switching voltage pin. The proposed switched resonator introduces one pole before the parallel resonance frequency, which sharpens the skirt characteristics of the scattering parameters of the resonator. The chip is implemented in the 0.18-μm CMOS technology, and the proposed VCO operates in four different frequency bands, with a total frequency tuning range (FTR) of 10.7%. The first band ranges from 19.4 to 19.84 GHz, the second band ranges from 19.8 to 20.3 GHz, the third band ranges from 20.25 to 20.73 GHz, and the fourth band ranges from 20.7 to 21.3 GHz. The VCO core circuit draws a dc current of 5 mA from a 1.8-V supply and achieves a PN of -110.7 at 1-MHz offset from a 20.25-GHz carrier. This proposed oscillator achieved a figure of merit (FoM) of -186.8 dBc/Hz, while the FoM taking account of the tuning voltage (FoM $^{{T/V}})$ is -181.4 dBc/Hz.

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$ . The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range.

Three-level (3L) inverters suffer from higher parasitic inductance due to the increased number of series-connected switches in a single current commutation loop (CCL) results in a larger size of CCL compared to their two-level (2L) counterparts. As such, semiconductors are subjected to higher voltage stress and severe ringing at the switching transient. While silicon carbide's (SiC) faster switching speed improves overall efficiency by reducing switching loss, the faster voltage, and current gradient (d v /d t and d i /d t ) generate electromagnetic interference (EMI) noise, requiring a larger and complicated filter stage design. To solve this problem, an optimized 3L T-type neutral point clamped power module has been proposed with a hybrid combination of the switch (SiC mosfet + Si IGBT) rated for 1200 V/160 A. Two direct bonded copper (DBC) substrates have been stacked to have a vertical power loop using laser-drilled vias, which provides low commutation loop inductance as low as 4.6 nH for the major CCLs including the wire bond. Other associated CCLs have also been identified and optimized. Additional DBC in the package will be acting as an EMI shield. The EMI noise has been compared to a traditional power module and a 21 dB reduction of common-mode noise has been observed.

A reconfigurable LO-generator (LOG) using an integer divider and a mixed-mode fractional divide-by-2.5 (Div2.5) is presented to generate a spurious and oscillator pulling free output spectrum without additional digital calibration for cellular narrowband Internet of Things (NB-IoT). The proposed LOG includes a fractional divider to mitigate the pulling effect between the oscillator and the power amplifier. The designed fractional Div2.5 consists of a digital Div2.5 core, a duty cycle corrector (DCC), and an I/Q generator (I/Q-GEN). An adaptive bias circuit (ADB) is applied to compensate for process, voltage, and temperature (PVT) variations on delay circuits of the DCC and the I/Q-GEN by adjusting the supply voltage. The designed LOG is fabricated in the 28-nm CMOS process while consuming 40 mW, including ADPLL, digitally controlled oscillator (DCO), local oscillator (LO) distribution buffers, and dividers at 2 GHz. The measured phase noise of the Div2.5 LOG generating 2-GHz carrier frequency is -146.3 dBc/Hz at a 10-MHz offset. The measured fractional spurious tones are below -90 dBc without oscillator pulling effects for the 1.6~2.1-GHz output frequency.

A 16-GS/s single 1.2-V supply direct RF-sampling capacitive D/A converter for soft radio base-station applications is implemented in a 16-nm FinFET technology. Due to co-integration with a wideband on-chip matching network, the D/A converter (DAC) is capable of signal synthesis between 600 MHz and 8 GHz, with a measured peak RF output power of +5.6 dBm. The linearity required by cellular base-station applications is achieved by employing several analog-domain linearization techniques, yielding a two-tone intermodulation distortion of better than -70 dBc up to the first Nyquist frequency. When transmitting a true multiband signal covering an instantaneous bandwidth of 1 GHz, an adjacent channel leakage ratio (ACLR) of better than -69 dBc is achieved. Digital segment mismatch correction is shown to improve the linearity of a segmented DAC in deep digital backoff operation. A full-rate digital pre-distortion (DPD) method with efficient model identification is experimentally demonstrated. Using DPD, the design achieves an spurious free dynamic range (SFDR) of better than 72 dBc over the entire 0.6-6-GHz frequency range.

A low-voltage dual-band CMOS voltage-controlled oscillator (VCO) is fabricated in a 90-nm CMOS process. The performance of the proposed VCO is improved by winding a multi-function inductor with transformer feedback and parasitic capacitance-splitting techniques. The proposed VCO adopts a push-push node to obtain a second-harmonic signal strengthened by using the injection amplifier and the band-pass filter. The measured tuning ranges of the fundamental signal and second-harmonic signal are from 27.5 to 30.04 GHz and from 55 to 60.08 GHz, respectively. The measured phase noise of the fundamental signal of 28.26 GHz is -95.62 dBc/Hz and -111.5 dBc/Hz at 1-MHz and 10-MHz offsets, respectively. The measured phase noise of the second-harmonic signal of 56.52 GHz is -87.83 dBc/Hz and -107.9 dBc/Hz at 1-MHz and 10-MHz offsets, respectively. The core power dissipation is 7.08 mW from a 0.6-V supply. The figure-of-merits (FOMs) and FOMs with tuning range (FOMTs) at 1-MHz and 10-MHz offsets are -176.1 dBc/Hz, -172 dBc/Hz, -175 dBc/Hz, and -170.9 dBc/Hz, respectively, from the fundamental signal of 28.26 GHz. The FOMs and FOMTs at 1-MHz and 10-MHz offsets are -174.3 dBc/Hz, -174.4 dBc/Hz, -173.2 dBc/Hz, and -173.3 dBc/Hz, respectively, from the second-harmonic signal of 56.52 GHz.

An active inductor based on gyrator-C structure is proposed in this work. Voltage-controlled oscillator with wide frequency range and significant RF output power based on the proposed active inductor is presented in this work. The design of the voltage-controlled oscillator is carried out using UMC 180 nm RFCMOS technology. Post-layout simulations are carried out using Spectre RF in Cadence virtuoso. Voltage-controlled oscillator can be tuned from 500 MHz to 2.8 GHz suitable for multi-band transceiver design. The proposed design attains a frequency tuning range of 139.4%. VCO operates at a supply voltage of 1.8 V with a power consumption of 5.3 mW. Phase noise at a frequency offset of 1 MHz from carrier frequency of 2.4 GHz is − 94 dBc/Hz. VCO occupies an active area of $$200 \times 150\,\upmu \hbox {m}^{2}$$ . Figure of merit values that take into consideration RF output power and frequency tuning range are comparable to other VCO designs proposed in the literature. PVT analysis of the designed VCO is presented in this work.

Fractional and reference spurs appear at the output of a fractional PLL along with the carrier. In the proposed architecture, two PLLs are conjunctly implemented for spur reduction—one fractional and other integer—with their control voltages summed together for dual control. A very low value (1/100) of the fractional frequency division ratio is considered. A fractional sampler is introduced that places bandstop notches at very low frequencies and hence, loop bandwidth of the fractional PLL has to be lower than the first spur frequency. To alleviate the issue of high area requirement by the second-order loop filter capacitors in the fractional PLL, the charge pump is divided into two parts with high and low values of pump currents. The charge pump with the low pump current drives the loop filter network segment with the resistor; thus, the area of the capacitor in this network can be reduced. By simulation in 180 nm CMOS technology, it is observed that the largest fractional spurs are reduced from $$+19.2$$ to $$-66.2$$ dBc, and the reference spurs from $$-28.5$$ to $$-67.8$$ dBc. Monte Carlo simulations show best and worst case spurs at $$-73$$ and $$-69$$ dBc, respectively. The architecture shows the phase noise characteristics of the integer PLL when identical oscillators are used in both the loops.

We propose and demonstrate a photonic delay line based carrier suppression interferometer system for measuring the phase noise of microwave sources. We show both theoretically and experimentally for the first time that carrier suppression is capable of suppressing the effects of the residual phase noise of the microwave amplifiers and the relative intensity noise of light in the system by up to 70 dB, and therefore effectively eliminates the contributions of these noise sources to the noise floor of the phase noise measurement system. Using a 2-km photonic delay line, we achieved phase noise measurement floors of −126 dBc/Hz at 1 kHz and −152 dBc/Hz at 10 kHz around a 10 GHz carrier, respectively, which are 15 and 20 dB lower than those of a frequency discriminator based phase noise measurement system using the same length of fiber delay and the same optical and microwave components. The noise floor of −152 dBc/Hz at 10 kHz is also 8 dB and 17 dB lower than those of a Keysight E5052B phase noise measurement system with 100-times cross-correlation and without cross-correlation, respectively. Even lower phase noise floors are expected for such a carrier suppression system if microwave phase shifters with lower residual phase noise or a longer photonics delay line are used.

Protein L affinity chromatography is a useful method for the purification of antibody fragments containing kappa light chains. In affinity chromatography, increasing the binding affinity leads to increased product purity, recovery, and dynamic binding capacity (DBC). In this study, molecular docking and molecular dynamics simulation techniques were used to design the engineered Protein L with higher affinity to the kappa light chain. Each engineered ligand was produced as a recombinant protein and coupled to a solid matrix. The purity, recovery, and DBC of the engineered resins were evaluated and then compared to those of a commercially available resin. The results showed important parameters for engineering more efficient Protein L ligands for affinity chromatography.