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This paper designs a fast, scalable and accurate architecture simulator (MVSim) for VLIW multi-core vector processors. The scalable VLIW multi-core vector processor model, multi-level storage architecture model and multi-core performance model are designed in MVSim. It implements cycle-accurate simulation of instruction set architectures, efficient functional simulation of Cache, DMA and multi-core synchronization, and uses multi-threading to achieve efficient and scalable simulation of multi-core processors. The experimental results show that MVSim can accurately simulate the program execution of the target multi-core processor, the simulation results are completely correct, and it has good scalability. The average simulation speed of MVSim is 227 times and 5 times faster than RTL simulator and CCS, respectively, and the average performance error is about 2.9%. [ABSTRACT FROM AUTHOR]

Sparse convolutional neural network (SCNN) accelerators eliminate unnecessary computations and memory access by exploiting zero-valued activation pixels and filter weights. However, data movement between the multiplier array and accumulator buffer tends to be a performance bottleneck. Specifically, the scatter network, which is the core block of SCNN accelerators, delivers Cartesian products to the accumulator buffer, and certain products are not immediately delivered owing to bus contention. A previous SCNN-based architecture eliminates bus contention and improves the performance significantly by making use of different dataflows. However, it relies only on weight sparsity, and its performance is highly dependent on the workload. In this paper, we propose a novel scatter network architecture for SCNN accelerators. First, we propose network topologies (such as window and split queuing), which define the connection between the FIFOs and crossbar buses in the scatter network. Second, we investigate arbitration algorithms (such as fixed priority, round-robin, and longest-queue-first), which define the priorities of the products delivered to the accumulator buffer. However, the optimization of the scatter network architecture alone may not be able to provide sufficient performance gain since it does not help to reduce bus contention itself. In this paper, we propose a cubic-constrained bank allocation for the accumulator buffer, which reduces bus contention without any increase in the hardware area. Based on the results of cycle-accurate simulation, register-transfer-level (RTL) design, and logic synthesis, this study investigates the trade-off between the performance and complexity of SCNN accelerators. In detail, it is verified that, when the optimized SCNN accelerators are applied to AlexNet, the proposed scatter network architecture can remove most of the performance degradation due to bus contention, thereby improving the accelerator performance by 72%, with an area increase of 18%. It is also shown that the proposed bank allocation provides an additional performance gain of up to 31% when it is applied to SqueezeNet. The proposed scatter network architectures and bank allocation can eliminate bus contention in most Cartesian product-based accelerators, regardless of the workload, without changing accelerator components other than the scatter network.

The static power consumption of networks-on-chip (NoCs) has been increasing across each technology generation. Power-gating is a very promising approach that can dramatically reduce NoC static power but may potentially cause substantial performance penalty. Significant research is needed to explore effective ways of applying power-gating to NoC routers. To enable further research advancement, cycle-accurate NoC power-gating simulation infrastructure is much needed. In this work, we identify key requirements for NoC power-gating simulation and discuss three important optimizations that can enable such simulators to handle router pipeline draining and handshaking correctly and efficiently. We also propose Agate , an effective NoC power-gating simulator that satisfies the key requirements and optimizations. It can be integrated into Gem5 for closed-loop, full-system simulation of NoC-based many-core computing systems. We demonstrate the capability of Agate by simulating and evaluating several power-gating schemes, including the recently proposed Power Punch power-gating scheme. [ABSTRACT FROM AUTHOR]

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures. [ABSTRACT FROM AUTHOR]

Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these devices, the typical role of PLCs in automation systems becomes restricted to a simple controller, since applications with more sophisticated computational requirements tend to be handled by external processing units along with the PLCs. To solve this issue, this work improves novel architecture proposals based on data flow machines, circuit simulation theory, and the memoization technique to achieve a performance boost based on the scan time reduction. Along with the architectural improvements, this paper evaluates the impact of different execution units' types and quantities in a cycle-accurate simulator (CAS) that was specially developed to simulate the PLC cores. Furthermore, in order to perform a robust and complete evaluation, the silicon areas of the simulated architectures are calculated using the McPAT framework to establish the performance/area relationship of the simulated cores. Evaluation results show best scan time reductions of up to 68% for cores with single execution units and up to 89% for cores with multiple execution units, as well as a best-case of 50% scan time reduction with an acceptable impact on the silicon area. Lastly, the evaluation of the results of the proposed improved cores with multiple execution units shows that they outperform the theoretical performance limit of multiple execution units based on Amdahl's law up to 4 execution units. [ABSTRACT FROM AUTHOR]