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Abstract Herein, a variable switching frequency pulse width (VSFPWM) modulation strategy for quasi‐Z‐source inverter (qZSI) based on a recently proposed modulation method, named as ZSVM8, is proposed. The formulae of quasi‐Z‐source inverter inductor current ripple of ZSVM8 are deduced in detail, and a prediction model for the current ripple is obtained. Combining with the VSFPWM technique, an improved modulation method named ZSVM8 VSFPWM is proposed to further reduce the switching times without increasing the maximum inductor current ripple. As a result, the switching losses can be reduced compared with the conventional ZSVM8. Besides, ZSVM8 VSFPWM also suppresses electromagnetic interference noise, such as current EMI and common‐mode voltage. Simulations and hardware experimental results are implemented to verify the efficacies of the proposed modulation method.

The input current ripple problem of DC/DC converters receives more and more attention recently. To meet the increasingly demanding requirements, the fundamental components of the current ripple are researched and the corresponding current ripple reduction methods are proposed in this paper. On the one hand, due to the imbalance between the input and output power of the whole system when connected to the grid, the 100-Hz bus voltage ripple is induced. If the bus voltage ripple cannot be regulated effectively, the 100-Hz ripple will be reflected in the DC input side. On the other hand, with low pulse-width modulation (PWM) resolution, the quantized error of digital control is accumulated, which causes the quantized input current ripple. The 100-Hz ripple and the quantized ripple are the main input current ripple components. To solve the problems, a small-signal model of the DC/DC converter is built to calculate the input current ripple mathematically. Based on the theoretical analysis, the proportional–integral–differential-resonant (PIDR) control is proposed and high-resolution pulse-width modulation (HRPWM) technology is applied. Finally, a 2-kW bidirectional DC/DC converter prototype is built. According to the experiments, the current ripple is reduced dramatically by 81.5% at full load with the proposed current ripple reduction methods.

In the finite control set model predictive control (FCS-MPC) strategy of the grid-tied inverter, the current ripple (CR) affects the selection of optimal voltage vectors, which leads to the increase of output current ripples. In order to solve this problem, this paper proposes a CR reduction method based on reference current compensation (RCC) for the FCS-MPC strategy of grid-tied inverters. Firstly, the influence of the CR on optimal voltage vector selection is analyzed. The conventional CR prediction method is improved, which uses inverter output voltage and grid voltage to calculate current ripples based on the space state equation. It makes up for the shortcomings that the conventional CR prediction method cannot predict in some switching states. The improved CR method is more suitable for the FCS-MPC strategy. In addition, the differences between the two cost functions are compared through visual analysis. It is found that the sensitivity of the square cost function to small errors is better than that of the absolute value function. Finally, the predicted CR is used to compensate the reference current. The compensated reference current is substituted into the square cost function to reduce the CR. The experimental results show that the proposed method reduces the CR by 47.3%. The total harmonic distortion (THD) of output current is reduced from 3.86% to 2.96%.

Herein, a variable switching frequency pulse width (VSFPWM) modulation strategy for quasi‐Z‐source inverter (qZSI) based on a recently proposed modulation method, named as ZSVM8, is proposed. The formulae of quasi‐Z‐source inverter inductor current ripple of ZSVM8 are deduced in detail, and a prediction model for the current ripple is obtained. Combining with the VSFPWM technique, an improved modulation method named ZSVM8 VSFPWM is proposed to further reduce the switching times without increasing the maximum inductor current ripple. As a result, the switching losses can be reduced compared with the conventional ZSVM8. Besides, ZSVM8 VSFPWM also suppresses electromagnetic interference noise, such as current EMI and common‐mode voltage. Simulations and hardware experimental results are implemented to verify the efficacies of the proposed modulation method. [ABSTRACT FROM AUTHOR]

Generally, discontinuous pulsewidth modulation (DPWM) strategy used in single Vienna rectifier will result in large current ripple and neutral-point fluctuation. When applied in interleaved rectifier, the issue of neutral-point voltage still exists. Besides, the input current around zero-crossing point is distorted due to the characteristics of unidirectional topology. Hence, a novel hybrid DPWM (H-DPWM) strategy for parallel Vienna rectifier is proposed in this article to reduce the distortion, current ripple, and neutral-point fluctuation. In this article, the characteristics of current ripple and neutral-point fluctuation with traditional DPWM (T-DPWM) are clarified at first. Then, the quantitative analyses on current ripple and neutral-point fluctuation with T-DPWM, classical space vector modulation, and optimized DPWM (O-DPWM) are presented in detail. To solve the issue of current distortion, the H-DPWM is proposed based on O-DPWM. Furthermore, the switching losses of these modulations are evaluated. At last, the analyses and performance of the proposed H-DPWM are verified by the experiments. [ABSTRACT FROM AUTHOR]

The instantaneous output power of the two-stage single-phase inverter pulsates at double-line frequency, generating a large amount of second harmonic current (SHC) in the front-end dc-dc converter and input dc source. The SHC is harmful to the system performance. To address the issue, a control strategy based on port-impedance editing, where inductor current feedforward (ICFF) and bus voltage feedforward paths are employed, is proposed to reduce the low frequency ripple in the article. Due to only bandpass filter employed in each feedforward path, the proposed control scheme is relatively easy to be implemented. Under the control strategy, the dc-bus port-impedance of dc-dc converter is increased rapidly at double-line frequency, while staying low impedance for other frequencies. What is more, different ICFF paths are taken into insight to obtain optimized path. Meanwhile, the small signal model of front-end dc-dc converter is established and the design principle of key parameters is provided for the derived control strategy. Furthermore, the dynamic response with bandwidth limitation is also discussed in this article. Finally, a two-stage single-phase inverter prototype was fabricated and tested. The experimental results verify the performance of the proposed strategy with SHC reduction. [ABSTRACT FROM AUTHOR]

This article investigates the matrix coupled “all-in-one” magnetic structure that combines both series coupling and parallel coupling for pulse-width modulated (PWM) power conversion. A systematic analysis of the current ripple reduction mechanism is performed. Current ripple steering among asymmetric series coupled windings is discussed. The transient performance of the matrix coupled inductor is demystified, providing insights for analyzing converter dynamics and its large- or small-signal modeling. To quantify the benefits of matrix coupling, a figure of merit is defined by comparing the current ripple of a matrix coupled inductor to that of a discrete inductor given the same transient speed. The comparison results indicate that a higher number of phases and a stronger matrix coupling coefficient amplify the benefits of matrix coupling. A 1 V-to-5 V input, 1 V-to-5 V output, four-phase matrix coupled synchronous SEPIC converter with planar PCB integrated magnetics is built and tested. The matrix coupled SEPIC prototype can support load current up to 185 A at 5 V-to-1 V voltage conversion with a maximum power density over 470 W/in $^\text{3}$. Compared to commercial discrete inductors, the matrix coupled inductor has a 5.6 times smaller size and 8.5 times faster transient speed with similar current ripple and current rating. The experimental results validate the matrix coupling concept and the theoretical analysis, opening the possibilities toward wide adoption of ‘‘all-in-one-magnetics” in PWM topologies. [ABSTRACT FROM AUTHOR]

The performance up-gradation that enhances the power output of the solar photovoltaic (SPV) panel along with life term is the latest demand in any standalone applications. The current ripple rejected to the SPV panel has both electrical and thermal effects. Lower the ripple, lower will be the power loss and the rise in temperature. Here, a method for an additional ripple current reduction at the source is demonstrated with a 300 W, 500 kHz, gallium nitride device-based panel integrated three-phase synchronous boost converter. A simple procedure of listing the switching states at each ON and OFF of polyphase periods in the analytical method for ripple estimation is proposed. A novel input current ripple reduction method, in addition to that of conventional operations, which leads the converter operations with minimum ripple rejection implemented. The factors that enhance the life of the SPV system, accomplishment of a typical improvement of 7% with a reduction of 3.5 deg. C rise in temperature, for all electrical reflections of the converter, is evaluated. Additionally, the electrical performance of 96.4% efficiency and 3.90 × 106 W/m3 power density was achieved. An SPV module integrated converter for a LED street-lighting application, implemented with the proposed method is detailed. [ABSTRACT FROM AUTHOR]

This paper presents a new hybrid dual-loop control system for the DC/DC LLC resonant converter, operating as a downstream DC/DC converter in a two independent stage offline LED driver. The outer loop employs a PI controller to maintain the average LED current regulated at the reference value and reject parametric variation. The inner loop implements an adaptive periodic disturbance rejection (APDR) subsystem, thus conceiving the hybrid PI\&APDR controller. The APDR subsystem is designed to strictly reject the bus voltage ripple and limit its transmission to the LED current. Experimental results show the proposed controller feasibility in achieving good tracking behavior, reduced output current ripple under different bus voltage ripple amplitude and frequency, robustness against parametric variations, and simple implementation and design. For the sake of completeness, the proposed PI&APDR is compared with the conventional proportional resonant controller employing experimental results and extra analysis based on simulations.

Torque ripple reduction is one of the major challenges in switching table-based direct torque control (DTC) while operating for open phase faults of an induction motor, as the switching vectors are unevenly distributed. This can be minimized by increasing the level of the inverter and with the use of multi-phase motors. Fuzzy logic-based DTC is another solution to the above problem. In this paper, a comparative analysis is done between switching table-based DTC (ST-DTC) and fuzzy logic-based DTC for increasing the performance during open phase faults of a five-phase induction motor. The result shows that in fuzzy logic-based DTC with a two-level inverter, the torque ripple is reduced by 5.164% as compared with ST-DTC with a three-level inverter. The fuzzy logic-based DTC with the three-level inverter also gives better performance as compared with fuzzy logic-based DTC with the two-level inverter. The current ripple also reduced by 9.605% with respect to ST-DTC. Thus, fuzzy logic-based DTC is more suitable and cost effective for open phase fault-tolerant drives. [ABSTRACT FROM AUTHOR]

In this article, a high-gain bidirectional quadratic dc–dc converter is proposed. This converter is studied under step-up and step-down modes. In each power flow direction, two switches and two antiparallel diodes of the other switches operate. Therefore, the switching losses depend only on the operation of two switches in each direction. The use of coupled inductor in the proposed converter significantly reduces the input and output current ripples of the step-up and step-down modes, respectively, at all operating points of continuous and discontinuous conduction modes (CCM and DCM). The voltage gain of the proposed converter in the step-up mode is as high as that of the cascaded boost converter, and in the step-down mode, the converter voltage gain is similar to that of the cascaded buck converter. Thus, the high-voltage conversion ratio with an appropriate duty-cycle in both power flow directions can be achieved. The operating principles and steady-state analysis of the proposed converter in CCM, DCM, and the boundary-conditions between these modes are discussed in detail. Finally, a prototype of the converter is implemented in the laboratory and the experimental results are presented to validate the effectiveness of the proposed converter. [ABSTRACT FROM AUTHOR]

Convectional optimal pulsewidth modulation (PWM) current ripple reduction methods divide the vector space sectors into subsectors, where the reference vector is synthesized with a theoretically optimal sequence. However, extra CPLD/FPGA is needed for the lookup table and the PWM signal generation for alternative sequences. Moreover, when swapping in between sequences, extra switching and losses are introduced, which is particularly significant for low sample ratio operations. This article starts with an intuitive perspective on the sequence for current ripple reduction. Then, an online method is proposed to dynamically compute and select the sequence with the lower current ripples throughout the vector space. The proposed stationary frame current ripple vector locus peak computation and comparison methods can be efficiently implemented in DSPs. The proposed online method is equally effective in ripple reduction as the CPLD/FPGA based offline-optimized methods. Moreover, with low sample ratio commonly used in practice, the proposed method has even less switching losses, as it avoids extra switching during the sequences swapping. Elaborate lab setup makes it possible to obtain the switching losses of the previous methods over wide ranges of motor drive operation. Thereby, the switching losses advantages of the proposed method are validated. [ABSTRACT FROM AUTHOR]

Input current around zero-crossing point is distorted and the reduction of current ripple is limited when applying space-vector modulation (SVM) to the interleaved Vienna rectifier. In this article, a hybrid SVM method for two- channel interleaved Vienna rectifier is developed to reduce the harmonics distortion and current ripple. The topology of two-channel interleaved Vienna rectifier is introduced. The current distortion around the zero-crossing point and the ripple characteristics around the peak of the current with SVM are analyzed. Then, a zero-crossing clamped method is used to eliminate the current distortion in the sectors around the zero-crossing point. To reduce the current ripple, the phase-shifted angle of the carriers between two channels is modified in the sectors around the peak of the current. Furthermore, the realization of the proposed hybrid SVM method is presented in details. With the proposed hybrid SVM method, the current distortion is attenuated and the current ripple amplitude is reduced obviously without increasing the switching frequency. Finally, the performance of the proposed method is compared with the classical SVM methods in a two-channel interleaved Vienna rectifier prototype. [ABSTRACT FROM AUTHOR]

The predictive current control (PCC) for an indirect matrix converter (IMC) with reduced current ripple is presented in this study. In the proposed PCC scheme, an IMC drives a load applying a split switching vector, which is used as a candidate vector of the cost function. The cost function of the proposed PCC includes a reference state and a predicted state. With the two states, the optimal output vector can be selected from the split switching vectors, thus alleviating the current ripples on both the grid side and the load side of the IMC. However, the use of the split switching vector increases the computation complexity of the cost function optimization because the number of predicted states is increased by the split switching vectors. Hence, the computation complexity reduction method in a deadbeat fashion is proposed for the simple implementation of the proposed PCC on a digital signal processor. In addition, the unity power factor on the grid side is guaranteed by a straightforward modulation technique when the maximum voltage is transferred. The performance of the proposed PCC for the IMC is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Power converter units are crucial components in proton exchange membrane fuel cell (PEMFC) energy generation systems. For this reason, and also motivated by the demands in high quality power conditioning for PEMFC systems, we propose the application of an interleaved high gain boost converter topology with a diode clamped multilevel inverter as power interface. The main advantages of the proposed scheme encompass: high voltage conversion ratio, input current ripple mitigation, and voltage balancing across output capacitors. These characteristics make this converter ideal for grid-connection purposes, acting as an interface for renewable energy sources that provide low voltages and demand low current ripples. The underlying theoretical analysis as well as simulation and experimental validation are presented in this paper. • A new dc-dc electronics converter for power conditioning of a fuel cell is proposed. • High-voltage gain is supplied for the proposed converter. • A design methodology for the power electronics converter is provided. • Experimental results validate the theoretical analysis stated. [ABSTRACT FROM AUTHOR]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

SUMMARY: This paper proposes a new drive circuit for reducing the switching current ripples in a switched reluctance motor (SRM). The authors have already presented an instantaneous flat torque control for SRMs, and confirmed its effectiveness through experimental results. However, the switching current ripples also cause torque ripples, and therefore, the current ripples should be decreased to reduce the torque ripples even more. The proposed circuit with parallel capacitor can realize such a reduction. The validity of the proposed drive circuit is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposes an improved offset selection method for discontinuous-pulse-width-modulation (DPWM)-based back-to-back converters to reduce dc-link current ripple. DPWM is introduced to power converters to diminish the stress on power transistors and prolong their lifespan. However, when using the DPWM method, the dc-link current ripple is increased in nonswitching regions of the power transistors. Moreover, in DPWM-based back-to-back converters, the dc-link current ripple reaches its maximum when the two transistors of both inverters are clamped in opposite directions. Therefore, the dc-link capacitors endure more stress, resulting in decreased life duration. To overcome this issue, the switching method should consider the clamping periods, when the current ripple increases. This can be achieved by modifying the DPWM offset, so that the clamping states of both converters are matched. The effectiveness of the proposed method is confirmed by both simulation and experimental results. [ABSTRACT FROM PUBLISHER]

A large amount of ripple at twice the output frequency will emerge in the input current due to the pulsating output power in a two-stage single-phase inverter. To reduce the low-frequency input current ripple, a control strategy is presented in this paper based on the front-end dc–dc converter load current feedforward. It intends to control the dc bus voltage to swing properly at twice the output frequency, making the dc bus capacitor supply nearly all the pulsating power. The implementation method is illustrated, and the operation performance analysis as well as the key parameter design principle is provided. Introducing the proposed feedforward path is able to significantly suppress the input current ripple with little impacts on the original system stability, steady-state tracking accuracy, and dynamic response. Finally, experimental results performed on a buck-type stand-alone two-stage single-phase inverter prototype verify the validity of proposed method and the correctness of analysis. [ABSTRACT FROM PUBLISHER]

Switching power amplifier is an essential component for magnetic bearing system. However, the current ripple resulted from the conduction and shutoff operation of power switch component inevitably affects the performance of active magnetic bearing. To reduce the current ripple of switching power amplifier, the characteristics of current ripple are first analysed. In response to the spectrum character of current ripple, an online lifting wavelet transform de‐noising algorithm, unlike the conventional power filter circuit, is proposed in this study. Moreover, the sliding data window and an improved threshold function are introduced to realise the feasibility of online processing and to improve the de‐noising performance, respectively. Finally, plentiful comparative experiments, taking the magnetically suspended flywheel as subject, are implemented. The results illustrate that the proposed algorithm could dramatically reduce the current ripple and that the rotor displacement jitter and the vibration force are suppressed accordingly. [ABSTRACT FROM AUTHOR]

High voltage gain dc-dc converters are required in many industrial applications such as photovoltaic and fuel cell energy systems, high-intensity discharge lamp (HID), dc back-up energy systems, and electric vehicles. This paper presents a novel input-parallel output-series boost converter with dual coupled inductors and a voltage multiplier module. On the one hand, the primary windings of two coupled inductors are connected in parallel to share the input current and reduce the current ripple at the input. On the other hand, the proposed converter inherits the merits of interleaved series-connected output capacitors for high voltage gain, low output voltage ripple, and low switch voltage stress. Moreover, the secondary sides of two coupled inductors are connected in series to a regenerative capacitor by a diode for extending the voltage gain and balancing the primary-parallel currents. In addition, the active switches are turned on at zero current and the reverse recovery problem of diodes is alleviated by reasonable leakage inductances of the coupled inductors. Besides, the energy of leakage inductances can be recycled. A prototype circuit rated 500-W output power is implemented in the laboratory, and the experimental results shows satisfactory agreement with the theoretical analysis. [ABSTRACT FROM AUTHOR]

Employing an L-C-L filter cell to modify the half-bridge converter (HBC), a HBC with input current ripple reduction (HBC-CRR) is proposed. In addition to having low-voltage stress, lossless snubbing, and voltage-clamping features inherited from its predecessor, the proposed converter can shape input current waveform of HBC to a nonpulsating fashion. Consequently, the ripple and undesired harmonic components of the input current can be significantly reduced without adding a large input filter. These characteristics make it suitable for high frequency, high efficiency, high-input voltage, and low electromagnetic interference (EMI) dc distribution power conversion applications. In addition to the circuit analysis and design consideration, moreover, a proposed converter and a HBC with the same specification, 360–400-V input, 12-V/20-A output, and 100-kHz switching frequency, are built and tested for the purpose of the comparison. Several performance comparisons are made to demonstrate the superiority of the proposed converter over HBC. [ABSTRACT FROM AUTHOR]

A novel winding-coupled bidirectional dc/dc converter with zero-voltage-switching (ZVS) performance is proposed in this paper. In the low-voltage side, the parallel configuration is employed to share the large current and reduce the current ripple. In the high-voltage side, the series structure is adopted to sustain the high bus voltage and achieve large voltage ratio conversion. There are only two coupled inductors in the proposed interleaved bidirectional converter and their secondary windings are in series to serve as winding-coupled inductors. Furthermore, the two winding-coupled inductors can be integrated into a magnetic core to reduce the passive component numbers and improve the power density. Moreover, ZVS soft-switching operation is implemented for all the power switches to minimize the switching losses by introducing the active clamp scheme. In addition, the pulsewidth modulation plus phase-shift control strategy is employed to reduce the power MOSFET peak current and diminish the circulating losses. The duty cycle is applied to balance the voltages of both sides. The phase-shift angle is introduced to realize the power flow regulation. This decoupling control strategy is advantageous for bidirectional dc/dc conversion to realize high efficiency. Finally, a 1-kW prototype is built to verify the effectiveness of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper presents a three-phase pulsewidth modulation (PWM) technique for brushless dc motor (BLDCM) drives to reduce the commutation torque ripple. As compared to previous approaches, the presented technique does not require any torque observer and calculation of commutation time which may be sensitive to motor parameters and may require more calculation time. The commutation time for the presented technique is determined by a detection circuit which consists of simple comparator circuit. The experimental results derived from a field programmable gate array based controlled BLDCM drive show that the commutation current ripple can be significantly reduced by the presented PWM technique. [ABSTRACT FROM PUBLISHER]

A high-efficiency fuel cell power conditioning system with input current ripple reduction is proposed. The proposed system consists of a high-efficiency high-step-up current-fed resonant push-pull converter and a full-bridge inverter. The converter conserves inherent advantages of a conventional current-fed push-pull converter such as low input-current stress and high voltage conversion ratio. Also, a voltage-doubler rectifier is employed in order to remove the reverse-recovery problem of the output rectifying diodes and provide much higher voltage conversion ratio. The current ripple reduction control without an external component is suggested. Therefore, the proposed system operates in a wide input-voltage range with a high efficiency. By using a current-ripple reduction control, the input current ripple is furthermore reduced. A 1.5-kW prototype is implemented with input-voltage range from 30 to 70 V. Experimental results show that minimum efficiency at full load is about 92.5% and that ripple current is less than 2% of the rated input current. [ABSTRACT FROM AUTHOR]

A simplified model predictive current control (MPCC) for four‐switch three‐phase inverter (FSTPI)‐fed permanent magnet synchronous motor (PMSM) considering the periodic fluctuation of the capacitor voltages is proposed. After analysing the inherent features of the FSTPI‐fed PMSM system, an offset voltage vector and an ideal reference voltage vector are defined, which allows to deal with the reference voltage in the ideal voltage vector plane. Thus, the sector division is simplified. Furthermore, a concept of virtual duty cycle is introduced to employ an equivalent null vector in the MPCC in order to reduce the current ripples. Combining with a simple sector division, the active voltage vector and its virtual duty cycle are determined with only one prediction. Comparative experimental studies between the conventional and the proposed MPCC are executed to validate the feasibility of the proposed simplified MPCC. [ABSTRACT FROM AUTHOR]

The use of series‐resonant converters (SRCs) in light‐emitting diode (LED) drivers has increased due to its simplicity and high efficiency. Furthermore, the use of a SRC provides reduction of the low‐frequency ripple in the LED current, originated by the bus voltage ripple. Thus, an analysis of the SRC aiming to define a design methodology to improve the current ripple reduction provided by the SRC is proposed. Moreover, a discussion about the main factors that have influenced ripple reduction and the limits for this attenuation is presented, which have not been explored in the literature hither to. [ABSTRACT FROM AUTHOR]