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Background: Magnetic Resonance Imaging (MRI) is a highly demanded medical imaging system due to high resolution, large volumetric coverage, and ability to capture the dynamic and functional information of body organs e.g. cardiac MRI is employed to assess cardiac structure and evaluate blood flow dynamics through the cardiac valves. Long scan time is the main drawback of MRI, which makes it difficult for the patients to remain still during the scanning process. Objective: By collecting fewer measurements, MRI scan time can be shortened, but this undersampling causes aliasing artifacts in the reconstructed images. Advanced image reconstruction algorithms have been used in literature to overcome these undersampling artifacts. These algorithms are computationally expensive and require a long time for reconstruction which makes them infeasible for real-time clinical applications e.g. cardiac MRI. However, exploiting the inherent parallelism in these algorithms can help to reduce their computation time. Methods: Low-rank plus sparse (L+S) matrix decomposition model is a technique used in literature to reconstruct the highly undersampled dynamic MRI (dMRI) data at the expense of long reconstruction time. In this paper, Compressed Singular Value Decomposition (cSVD) model is used in L+S decomposition model (instead of conventional SVD) to reduce the reconstruction time. The results provide improved quality of the reconstructed images. Furthermore, it has been observed that cSVD and other parts of the L+S model possess highly parallel operations; therefore, a customized GPU based parallel architecture of the modified L+S model has been presented to further reduce the reconstruction time. Results: Four cardiac MRI datasets (three different cardiac perfusion acquired from different patients and one cardiac cine data), each with different acceleration factors of 2, 6 and 8 are used for experiments in this paper. Experimental results demonstrate that using the proposed parallel architecture for the reconstruction of cardiac perfusion data provides a speed-up factor up to 19.15× (with memory latency) and 70.55× (without memory latency) in comparison to the conventional CPU reconstruction with no compromise on image quality. Conclusion: The proposed method is well-suited for real-time clinical applications, offering a substantial reduction in reconstruction time. [ABSTRACT FROM AUTHOR]

Data-parallel computations, such as linear algebra routines and stencil computations, constitute one of the most relevant classes in parallel computing, e.g., due to their importance for deep learning. Efficiently de-composing such computations for the memory and core hierarchies of modern architectures and re-composing the computed intermediate results back to the final result—we say (de/re)-composition for short—is key to achieve high performance for these computations on, e.g., GPU and CPU. Current high-level approaches to generating data-parallel code are often restricted to a particular subclass of data-parallel computations and architectures (e.g., only linear algebra routines on only GPU or only stencil computations), and/or the approaches rely on a user-guided optimization process for a well-performing (de/re)-composition of computations, which is complex and error prone for the user. We formally introduce a systematic (de/re)-composition approach, based on the algebraic formalism of Multi-Dimensional Homomorphisms (MDHs). Our approach is designed as general enough to be applicable to a wide range of data-parallel computations and for various kinds of target parallel architectures. To efficiently target the deep and complex memory and core hierarchies of contemporary architectures, we exploit our introduced (de/re)-composition approach for a correct-by-construction, parametrized cache blocking, and parallelization strategy. We show that our approach is powerful enough to express, in the same formalism, the (de/re)-composition strategies of different classes of state-of-the-art approaches (scheduling-based, polyhedral, etc.), and we demonstrate that the parameters of our strategies enable systematically generating code that can be fully automatically optimized (auto-tuned) for the particular target architecture and characteristics of the input and output data (e.g., their sizes and memory layouts). Particularly, our experiments confirm that via auto-tuning, we achieve higher performance than state-of-the-art approaches, including hand-optimized solutions provided by vendors (such as NVIDIA cuBLAS/cuDNN and Intel oneMKL/oneDNN), on real-world datasets and for a variety of data-parallel computations, including linear algebra routines, stencil and quantum chemistry computations, data mining algorithms, and computations that recently gained high attention due to their relevance for deep learning. [ABSTRACT FROM AUTHOR]

Cruise machinists operate in dynamic and physically demanding environments where improper posture can lead to musculoskeletal disorders, adversely affecting their health and work efficiency. Current ergonomic assessments in such settings are often generic and not tailored to the unique challenges of maritime operations. This paper presents a novel application of artificial intelligence tools for real-time posture estimation specifically designed for cruise machinists. The primary aim is to enhance occupational health and safety by providing precise, real-time feedback on ergonomic practices. We developed a dataset by capturing video recordings of cruise machinists at work, which were processed to extract skeletal outlines using advanced computer vision techniques. This dataset was used to train deep neural networks, optimizing them for accuracy in diverse and constrained shipboard environments. The networks were tested across various computational platforms to ensure robustness and adaptability. The AI model demonstrated high efficacy in recognizing both correct and incorrect postures under real-world conditions aboard ships. The system significantly outperformed traditional ergonomic assessment tools in terms of speed, accuracy, and the ability to provide instant feedback. The findings suggest that AI-enhanced ergonomic assessments could be a transformative approach for occupational health across various industries. [ABSTRACT FROM AUTHOR]

The unprecedented increase in interconnected data has driven the development of efficient graph analytics for extensive data analysis, resulting in improvements across various domains. Prior work has focused on optimizing graph execution for both CPUs and GPUs while overlooking the scalability of graph applications and the selection of an ideal architecture. Thus, we propose Allok, a flexible graph processing framework that aids in selecting the optimal processing architecture (CPU or GPU) for a batch of graph applications while also optimizing number of threads on CPUs. Allok relies solely on high-level graph features to make decisions without the need for further application execution. Our experiments on an HPC system with 4 CPUs and 3 GPUs running 5 algorithms over 25 input graphs show that Allok reduces application execution time by an average of 67.26 × and reduces energy consumption and energy-delay product by an average of 18.06 × and 1237.96 × , respectively. [ABSTRACT FROM AUTHOR]

Cruise machinists operate in dynamic and physically demanding environments where improper posture can lead to musculoskeletal disorders, adversely affecting their health and work efficiency. Current ergonomic assessments in such settings are often generic and not tailored to the unique challenges of maritime operations. This paper presents a novel application of artificial intelligence tools for real-time posture estimation specifically designed for cruise machinists. The primary aim is to enhance occupational health and safety by providing precise, real-time feedback on ergonomic practices. We developed a dataset by capturing video recordings of cruise machinists at work, which were processed to extract skeletal outlines using advanced computer vision techniques. This dataset was used to train deep neural networks, optimizing them for accuracy in diverse and constrained shipboard environments. The networks were tested across various computational platforms to ensure robustness and adaptability. The AI model demonstrated high efficacy in recognizing both correct and incorrect postures under real-world conditions aboard ships. The system significantly outperformed traditional ergonomic assessment tools in terms of speed, accuracy, and the ability to provide instant feedback. The findings suggest that AI-enhanced ergonomic assessments could be a transformative approach for occupational health across various industries.

The high-resolution DEM-IMB-LBM model can accurately describe pore-scale fluid-solid interactions, but its potential for use in geotechnical engineering analysis has not been fully unleashed due to its prohibitive computational costs. To overcome this limitation, a message passing interface (MPI) parallel DEM-IMB-LBM framework is proposed aimed at enhancing computation efficiency. This framework utilises a static domain decomposition scheme, with the entire computation domain being decomposed into multiple subdomains according to predefined processors. A detailed parallel strategy is employed for both contact detection and hydrodynamic force calculation. In particular, a particle ID re-numbering scheme is proposed to handle particle transitions across sub-domain interfaces. Two benchmarks are conducted to validate the accuracy and overall performance of the proposed framework. Subsequently, the framework is applied to simulate scenarios involving multi-particle sedimentation and submarine landslides. The numerical examples effectively demonstrate the robustness and applicability of the MPI parallel DEM-IMB-LBM framework.

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff. [ABSTRACT FROM AUTHOR]

With the advancements in electronic systems, efficient cooling has become an exciting task in thermal grounds. For optimum working conditions of electronic systems energy-efficient a heat sink is used. In the present paper, thermal simulation is carried out on two different profiles of existing heat sinks used in the processor. Six different cases were studied and compared namely natural and forced convection on circular and rectangular heat sinks with and without FGM (Functionally Graded Materials.) Conventional material aluminium alloy 6061 and functionally graded material AlSi10Mg are used to understand the variation of temperature of the heat sink by applying the necessary boundary conditions for the heat sink profile. The energy model and finite volume method have been used for investigation using ANSYS software. In comparison between the two heat sink profiles, it is witnessed that the circular heat sink dissipates more heat. From the thermal analysis, it is found that using FGM will improve the heat transfer rate, and the temperature variation is found to be 3oC in comparison with conventional material because FGM is inhomogeneous materials consisting of two or more materials. [ABSTRACT FROM AUTHOR]

FlowDenoising is a new approach to noise reduction in biological volumes obtained with three-dimensional electron microscopy (3DEM). Its abilities to enhance the structural features stem from the fact that an anisotropic Gaussian filtering is steered according to the local structures. To this end, the Optical Flow (OF) among consecutive slices is estimated, which is the most computationally expensive step in this approach. In this article, a hybrid CPU/GPU implementation of FlowDenoising is introduced and evaluated. It exploits parallel computing by distributing the workload among multiple cores and takes advantage of the massive processing in GPUs to accelerate the OF estimation. The hybrid implementation provides remarkable speed-up factors and an important reduction of the processing time, which is particularly relevant for the denoising of huge volumes typically found in 3DEM. [ABSTRACT FROM AUTHOR]

The Modular Multilevel Converter (MMC) is a promising converter for medium-/high voltage applications due to its various features. The waveform quality could be enhanced further by expanding the number of generated voltage levels, which increases the number of submodules (SMs); however, this improvement enlarges the size and cost of the converter, posing a persistent challenge. Hence, there exists a trade-off between power quality and the size and complexity of the converter. To verify the performance of such a complex converter and to validate the effectiveness of the control system, especially in the absence of a physical system, Real-Time (RT) simulation becomes crucial. However, the large number of components of a MMC creates important numerical challenges and computational difficulties in RT simulation. This paper proposes a grid-connected MMC employing a Z Packed U-Cell converter as a SM to generate a higher number of voltage levels while minimizing the required number of SMs. The ZPUC-MMC is implemented on an FPGA-based RT simulation platform using Electric Hardware Solver to reduce computational burden and simulation time, while improving the accuracy of the obtained results. Conventional controllers of MMCs are applied to assess the effectiveness and robustness of the proposed system during steady-state and dynamic operations. [ABSTRACT FROM AUTHOR]

The development of electronic devices is accompanied by the generation of significant heat. A novel plate-fins design with various orientation angles of 30°, 35°, 37.5°, 40° and 45° was studied. The plate-fins design aims to boost the performance by increasing the surface area and redirecting airflow towards the heat sink plate. The experimental results obtained by this work were employed to validate the numerical results for pin-fins heat sink. A three-dimensional computational domain was investigated using ANSYS Fluent 19.1. The air flow was turbulent and modelled using k-ω turbulent flow. The plate-fins with an orientation angle of 37.5ᴼ exhibit the optimum hydrothermal performance among other configurations. Equally, several optimisation parameters including the number of rows, the diameter and thickness of the pins and the width of the plate-fins were investigated. It was observed that the heat sink with two rows of plate-fins outperformed other designs. This configuration resulted in a significant reduction of 2 % in hot spot temperature and a notable reduction of 60.8 % in pressure drop.

Recently, shipborne radars are being developed into fully-digital Active Electronically Scanned Array (AESA) multifunctional radars (MFR) that are capable of electronic beam steering, simultaneously detecting and tracking multiple targets in a complex maritime environment, and performing electronic countermeasure functions in real-time. However, because the development process of a radar is expensive owing to its high complexity, using Simulated Signal Generator (SSG) that can emulate the function of an antenna proves effective in radar development. In this study, we propose a real-time implementation method for SSG capable of simulating maritime battlefield environments and targets using fully digital-based antenna simulation. We propose a CPUand FPGA-based real-time system architecture, fixed-point operation, real-time channel noise generation method, and real-time beamforming structure to generate modeling results that are presented. [ABSTRACT FROM AUTHOR]

In this paper we identify the causes of numerical non-reproducibility in the unstructured mesh computational motif, a class of algorithms commonly used for the solution of PDEs. We introduce a number of parallel and distributed algorithms to address nondeterminism in the order of floating-point computations, in particular, a new graph coloring scheme that produces identical coloring results regardless of how many parts the graph is partitioned to. We implement these in the OP2 domain specific language (DSL) and show how it can be automatically deployed to any application that uses OP2 without user intervention. We contrast differences in results without reproducibility and then demonstrate how bitwise reproducibility can be gained using our methods on a variety of applications including a production CFD application used at Rolls-Royce. We evaluate the performance and overheads of enforcing bitwise reproducibility on a cluster of CPUs and GPUs. [ABSTRACT FROM AUTHOR]

In view of the problem of Ethernet transmission rate and real-time in embedded field, a design of Gigabit Ethernet port communication based on FPGA(Field Programmable Gate Array)is proposed. This study designs the forwarding function of Gigabit Ethernet switch, and implements end-to-end data communication based on label forwarding. Datagrams with label are sent by CPU(Central Processing Unit), and are outputted through Gigabit Ethernet interface, and are sent to FPGA through RGMII(Reduced Gigabit Media Independent Interface)port. FPGA judges output port number field in label through internal logic and removes label, and outputs datagrams to connecting device from corresponding Gigabit Ethernet interface. Peripherals input datagrams through Gigabit Ethernet ports, and send datagrams to FPGA through SGMII(Serial Gigabit Media Independent Interface) protocol. FPGA adds labels through internal logic and outputs them to CPU through polling, so as to realize interworking of connecting devices of multiple Gigabit Ethernet interface. The experimental results reveal the feasibility and effectiveness of the FPGA logic. The transmission rate reaches 1 Gbit·s-1, the datagrams forwarding delay is less than 100 μs, and the packet loss rate is 0%,which indicates that the data transmission stability is high, and the proposed design meets the actual needs of existing projects. [ABSTRACT FROM AUTHOR]

The Craig–Bampton (CB) method is a well-known substructuring technique that reduces the size of a finite element model (FEM) using a set of vibration modes. For large FEA models, the reduction process could be computationally expensive since it requires algebra operations on FEM mode shapes and FEM system sparse matrices. In this paper, we investigate the potential of usage of GPU parallel processing to speed up solving the system of linear equations that results from the CB reduction process made for a model of cyclic structures. A Python based high-level approach, employing the CuPy, GinkGo and STRUMPACK libraries on the GPU, is compared with an optimized Fortran code. In side-to-side comparisons, employing the same inputs, the Python-GPU code is run on a single GPU device and the Fortran code is run on a multi-core compute node. The CB reduction process was split into several parts, each dealing with different kind of algebraic formulation of the problem. Performance comparisons were focused on the sparse system linear solver, since it turned out to be the most time-consuming part. The results suggest that the current GPU-based linear sparse solvers do not surpass the state-of-the-art CPU-based MKL PARDISO solver (at least up to 1M DOFs). [ABSTRACT FROM AUTHOR]

Effectively managing energy and power consumption is crucial to the success of the design of any computing system, helping mitigate the efficiency obstacles given by the downsizing of the systems while also being a valuable step towards achieving green and sustainable computing. The quality of energy and power management is strongly affected by the prompt availability of reliable and accurate information regarding the power consumption for the different parts composing the target monitored system. At the same time, effective energy and power management are even more critical within the field of devices at the edge, which exponentially proliferated within the past decade with the digital revolution brought by the Internet of things. This manuscript aims to provide a comprehensive conceptual framework to classify the different approaches to implementing run-time power monitors for edge devices that appeared in literature, leading the reader toward the solutions that best fit their application needs and the requirements and constraints of their target computing platforms. Run-time power monitors at the edge are analyzed according to both the power modeling and monitoring implementation aspects, identifying specific quality metrics for both in order to create a consistent and detailed taxonomy that encompasses the vast existing literature and provides a sound reference to the interested reader. [ABSTRACT FROM AUTHOR]

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In order for a computer to perform well, it is important to keep the central processing unit (CPU) cool, and this can be accomplished by using a liquid coolant. This study was conducted to investigate how effective nanofluids could be as a coolant for a water block used in CPU cooling. The nanofluids used in the experiment contained Al2O3 nanoparticles and SDS surfactant in a mixture in water at volume fractions of 0.5%. They were prepared using an ultrasonic cleaner, and then tested to determine how well they transferred heat and the amount of pump power needed. The findings suggest that nanofluids with higher concentrations have better convection coefficient values and are more efficient at reducing the temperature of the water block, but they require more pumping power. It was concluded that the Al2O3 nanofluid with SDS surfactant could be used as a coolant for CPU cooling because of its effectiveness in lowering the temperature of the water block. The present work results are agreed with data available in the literature.

In this paper, the design and the thermal analysis of a tribled microprocessor cooler combining the advantages of strong swirl flow and minichannel-fins and CuO nanofluid, have been presented. It is thought that the results will contribute to the understanding of the effects of parameters on the cooling flux of the heat sink and the decline at the microprocessor temperature, as Reynolds number in the minichannels and CuO % volume fraction. The results have exhibited that the total performance of the heat sink cooled with the mixture of water–CuO-EG nanofluids increases with the increase of Re number and the %load of nanoparticles in the coolant. It has been determined that the energy withdrawn from the microprocessor was 241 times higher than the energy generated for maximum CuO load and Re number conditions. Besides, the highest temperature decrease has been measured at the maximum CuO load value and maximum Re number.

In recent years, attention has been focused on failure prediction technology for electronic devices that can ensure the stable operation of the infrastructure, by warning the failure of devices before it happens, and noticing for an early maintenance which can minimize downtime. Different from the HDD, which is a storage medium, the research about the SoC or the CPU, which is an arithmetic unit, is few. One of the reasons is that the SoC or the CPU has a long life and a low failure rate, because of their smaller number of mechanical parts. Also, the number of SoCs or CPUs used in infrastructure control boards is small. Therefore, the problem is that it is difficult to obtain log data and failure data for the SoC or the CPU. Thus, the purpose of this research is to establish an accelerated test method that causes SoC to failure in a short time, with similar failure mode for those works in normal condition, and to acquire log data and failure data for the further development of failure prediction technology. By establishing a system that can locally heat the SoC to promote failure, it is possible to acquire a large amount of SoC failure data and log data in a short time. Finally, using the acquired 17 sets of failure data and log data, we tried to apply them to the failure prediction of the control board SoC. By using machine leaning algorithm OC-SVM, and using CPU calculation time as feature, it was showed that the failure of the SoC can be detected within 5% of the remaining life, with true detection rate of 47.1% and false detection rate of 17.6%. Based on this result, the failure prediction technology developed in this research was considered having a certain level of value in field using, by strengthening the redundancy system.

CPU computes several complex algorithms at billions of cycles per second. It is acceptable to generate some heat while working at such great speed. In order to reduce the problem of high temperature, which slows down the performance of tasks, a new heat sink with convex-parabolic fins was designed to study the best heat dissipation methods to reach the cooling efficiency of the processor so that it performs all tasks without any problems. On the other hand, the new heat sink was cooled by the hybrid nanofluid, and all the equations governing the phenomenon were solved by the finite volume method, and the results were reported at Reynolds numbers and fin numbers. From the results, the cooling efficiency was improved by 74% when a large number of fins were used. Besides that, the maximum temperature of the heat sink decreases by increasing the number of convex-parabolic fins, giving the processor a cool surface to perform tasks without having to fear the problem of overheating. The results of this study can be used for the initial design of the heat sink and the improvement in the efficiency of cooling the Core I7 CPU. [ABSTRACT FROM AUTHOR]

In the present article, we describe the implementation of the finite element numerical integration algorithm for the Xeon Phi coprocessor. The coprocessor was an extension of the many-core specialized unit for calculations, and its performance was comparable with the corresponding GPUs. Its main advantages were the built-in 512-bit vector registers and the ease of transferring existing codes from traditional x86 architectures. In the article, we move the code developed for a standard CPU to the coprocessor. We compare its performance with our OpenCL implementation of the numerical integration algorithm, previously developed for GPUs. The GPU code is tuned to fit into a coprocessor by our auto-tuning mechanism. Tests included two types of tasks to solve, using two types of approximation and two types of elements. The obtained timing results allow comparing the performance of highly optimized CPU and GPU codes with a Xeon Phi coprocessor performance. This article answers whether such massively parallel architectures perform better using the CPU or GPU programming method. Furthermore, we have compared the Xeon Phi architecture and the latest available Intel's i9 13900K CPU when writing this article. This comparison determines if the old Xeon Phi architecture remains competitive in today's computing landscape. Our findings provide valuable insights for selecting the most suitable hardware for numerical computations and the appropriate algorithmic design. [ABSTRACT FROM AUTHOR]

Finding the centrality measures of nodes in a graph is a problem of fundamental importance due to various applications from social networks, biological networks, and transportation networks. Given the large size of such graphs, it is natural to use parallelism as a recourse. Several studies show how to compute the various centrality measures of nodes in a graph on parallel architectures, including multi‐core systems and GPUs. However, as these graphs evolve and change, it is pertinent to study how to update the centrality measures on changes to the underlying graph. In this article, we show novel parallel algorithms for updating the betweenness‐ and closeness‐centrality values of nodes in a dynamic graph. Our algorithms process a batch of updates in parallel by extending the approach of handling a single update for betweenness‐ and closeness‐centrality. For the latter, we also introduce techniques based on traversals of the block‐cut tree of a graph. Besides, our algorithms incorporate mechanisms to exploit the structural properties of graphs for enhanced performance. We implement our algorithms on two parallel architectures: an Intel 24‐core CPU and an Nvidia Tesla V100 GPU. To the best of our knowledge, we are the first to show GPU algorithms for the above two problems. In addition, we conduct detailed experiments to study the impact of various parameters associated with our algorithms and their implementation. Our results on a collection of real‐world graphs indicate that our algorithms achieve a significant speedup over corresponding state‐of‐the‐art algorithms. [ABSTRACT FROM AUTHOR]

In order to improve the performance of the big data visualization platform and improve the task scheduling capability of the platform, a big data visualization platform is constructed based on Field Programmable Gate Array (FPGA) chip application power equipment. This study proposes to combine genetic algorithm and ant colony scheduling (ACOS) algorithm to design a big data visualization platform deployment strategy based on improved ACOS algorithm. Firstly, big data technology is analyzed. Then, the basic theory of ant colony algorithm is studied. According to the basic theory of ACOS and genetic algorithm, an improved ACOS algorithm model is constructed. The improved ACOS algorithm scheduler is compared with the other three schedulers. Under the same environment, the completion time of scheduling the same job and different task amounts is analyzed. The Central Processing Unit (CPU) utilization is analyzed when different schedulers completely different workloads. The results show that the constructed big data visualization platform based on the improved ACOS algorithm model has higher task scheduling efficiency than other schedulers, and can greatly shorten the data processing time. The experimental results show that under the homogeneous cluster, the completion time of the improved ACOS algorithm generally lags the capacity scheduler and the fair scheduler. Under the heterogeneous cluster, the improved ACOS algorithm scheduler can reasonably allocate tasks to nodes with different performances, reducing the task completion time. When the number of completed tasks increases from 50 to 200, the time increases by 45s, and the completion time is smaller than other schedulers. The CPU utilization of different task volumes is the highest, and the utilization rate increases from 81% to 95%. The improved ACOS algorithm scheduler has the shortest data processing time and the highest efficiency. This work provides a certain reference value for optimizing the deployment strategy of the big data visualization platform and improving the performance of the platform. [ABSTRACT FROM AUTHOR]

Cloud infrastructural resource optimization is the process of precisely selecting the allocating the correct resources either to a workload or application. When workload execution, accuracy, and cost are accurately stabilized in opposition to the best possible framework in real-time, efficiency is attained. In addition, every workload or application required for the framework is characteristic and these essentials change over time. But, the existing method was failed to ensure the high Quality of Service (QoS). In order to address this issue, a Tricube Weighted Linear Regression-based Inter Quartile (TWLR-IQ) for Cloud Infrastructural Resource Optimization is introduced. A Tricube Weighted Linear Regression is presented in the proposed method to estimate the resources (i.e., CPU, RAM, and network bandwidth utilization) based on the usage history in each cloud server. Then, Inter Quartile Range is applied to efficiently predict the overload hosts for ensuring a smooth migration. Experimental results show that our proposed method is better than the approach in Cloudsim under various performance metrics. The results clearly showed that the proposed method can reduce the energy consumption and provide a high level of commitment with ensuring the minimum number of Virtual Machine (VM) Migrations as compared to the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

Deep learning presents an efficient set of methods that allow learning from massive volumes of data using complex deep neural networks. To facilitate the design and implementation of algorithms, deep learning frameworks provide a high‐level programming interface. Based on these frameworks, new models, and applications are able to make better and better predictions. One type of deep learning application is the Internet of Things that can gather a continuous flow of data, which causes an explosion of the amount of data. Therefore, to handle this data management issue, computation technologies can offer new perspectives to analyze more data with more complex models. In this context, a cluster of computers can operate to quickly deliver a model or to enable the design of a complex neural network spread among computers. An alternative is to distribute a deep learning task with HPC cloud computing resources and to scale cluster in order to quickly and efficiently train a neural network. As a first step to design an infrastructure aware framework which is able to scale the computing nodes, this work aims to review and analyze the state‐of‐the‐art frameworks by collecting device utilization data during the training task. We gather information about the CPU, RAM and the GPU utilization on deep learning algorithms with and without multi‐threading. The behavior of each framework is discussed and analyzed in order to shed light on the strengths and weaknesses of the different deep learning frameworks. [ABSTRACT FROM AUTHOR]

The thermal performance of a novel hybrid nanofluid containing graphene oxide (GO)–gold/water and GO/water nanofluid in cooling a computer's CPU is carried out experimentally. Single-layer graphene oxide is used as working fluid by combining specific amounts of gold nanoparticle suspension with varying concentrations (0.0044–0.0114 mass%) and Reynolds number (676–2185) to optimize the overall device performance. The obtained results revealed that GO/water nanofluid and GO–gold/water hybrid nanofluid reduced the surface temperature of the CPU by 10.6% and 16.2%, respectively, compared with the DI water. Also, the results show that the convective heat transfer coefficient is improved by 36.36% with GO–gold/water hybrid nanofluid (0.0094 mass%) and Re = 2185. In addition, new correlations have been developed for predicting the Nusselt number of GO–gold/water hybrid nanofluid and GO/water nanofluid, based on the experimental data. Overall, the hybrid nanofluid is highly recommended as a preferred cooling in electronic devices. [ABSTRACT FROM AUTHOR]

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor's pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%. [ABSTRACT FROM AUTHOR]

We review the problem of automating hardware-aware architectural design process of Deep Neural Networks (DNNs). The field of Convolutional Neural Network (CNN) algorithm design has led to advancements in many fields, such as computer vision, virtual reality, and autonomous driving. The end-to-end design process of a CNN is a challenging and time-consuming task, as it requires expertise in multiple areas such as signal and image processing, neural networks, and optimization. At the same time, several hardware platforms, general-and special-purpose, have equally contributed to the training and deployment of these complex networks in a different setting. Hardware-Aware Neural Architecture Search (HW-NAS) automates the architectural design process of DNNs to alleviate human effort and generate efficient models accomplishing acceptable accuracy-performance tradeoffs. The goal of this article is to provide insights and understanding of HW-NAS techniques for various hardware platforms (MCU, CPU, GPU, ASIC, FPGA, ReRAM, DSP, and VPU), followed by the co-search methodologies of neural algorithm and hardware accelerator specifications. [ABSTRACT FROM AUTHOR]