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We like and need Information and Communication Technologies (ICTs) for data processing. This is measurable in the exponential growth of data processed by ICT, e.g., ICT for cryptocurrency mining and search engines. So far, the energy demand for computing technology has increased by a factor of 1.38 every 10 years due to the exponentially increasing use of ICT systems as computing devices. Energy consumption of ICT systems is expected to rise from 1500 TWh (8% of global electricity consumption) in 2010 to 5700 TWh (14% of global electricity consumption) in 2030 [A. S. G. Andrae, Eng. Appl. Sci. Lett. 3, 19–31 (2020)]. A large part of this energy is required for the continuous data transfer between separated memory and processor units, which constitute the main components of ICT computing devices in von-Neumann architecture. This, at the same time, massively slows down the computing power of ICT systems in von-Neumann architecture. In addition, due to the increasing complexity of artificial intelligence (AI) compute algorithms, since 2010, the AI training compute time demand for computing technology has increased tenfold every year, for example, from 1 × 10−6 to 1 × 10+4 Petaflops/day in the period from 2010 to 2020 [J. Wang, see https://ark-invest.com/articles/analyst-research/ai-training/ for information about the cost to train an AI interference system (2020)]. It has been theoretically predicted that ICT systems in the neuromorphic computer architecture will circumvent all of this through the use of merged memory and processor units. However, the core hardware element for this has not yet been realized so far. In this work, we discuss the perspectives for non-volatile resistive switches with hysteretic memristance as the core hardware element for merged memory and processor units in neuromorphic computers. [ABSTRACT FROM AUTHOR]

This letter presents the implementation of a polyphase digital down converter (DDC) that employs a least mean square (LMS) algorithm associated with particle swarm optimization (PSO) for the wideband code division multiple access (WCDMA) application. The PSO-based LMS algorithm suppresses the noise signal, enabling a significant improvement in the spurious-free dynamic range (SFDR), which is 130 dB. The complex multiplication is realized by the canonical impel-mentation to reduce the number of multipliers. The suggested polyphase DDC architecture is successfully implemented in the field-programmable gate array device (FPGA) Kintex-7 platform. To achieve high accuracy, the proposed design is implemented with an efficient user-defined floating-point representation data type. Synthesis results suggested that the design consumes less area and power compared to the most recent structure. [ABSTRACT FROM AUTHOR]

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by $2.1\times $ , latency by $40\times $ , and interconnect area by $2\times $ , compared to a state-of-the-art interconnect for neuromorphic systems. [ABSTRACT FROM AUTHOR]

Intelligent connected vehicles (ICVs) are the result of technological advancements in the new era, greatly enhancing the driving experience. However, due to the complex nature of the system, the intelligence of devices, and the connectivity of data, a complex physical fusion system has been created. The in-vehicle Telematics Box (T-Box), serving as the central communication and data hub, faces challenges, such as network vulnerabilities, data privacy, and malicious attacks through untrusted software updates. Therefore, an in-vehicle T-Box with high reliability, security, and performance is an urgent product in the era of the Internet of Vehicles. This article investigates the endogenous security of the T-Box in ICV, with a focus on the integration of dynamic heterogeneous redundancy (DHR) architecture. The underlying idea is to transform the original system into multiple heterogeneous systems, where some of them handle the same business functions. By applying a consensus mechanism to detect malicious nodes and dynamically scheduling healthy nodes into the working mode, a self-purifying defense system with intrinsic security is formed. This design approach endows the T-Box with inherent defense capabilities against unknown vulnerabilities. Meanwhile, the in-vehicle T-Box is redesigned in the software and hardware implementation scheme. Experimental results demonstrate that the new design notably enhances and ensures the robust stability and elevated reliability of the in-vehicle T-Box. Evidently, the upgraded T-Box ensures the safe processing of in-vehicle CAN bus data. [ABSTRACT FROM AUTHOR]

Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture; 2) an inverse NTT (INTT) architecture; and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit $4.66\times $ and $3.75\times $ higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve $1.25\times $ and $1.09\times $ higher throughput/area and energy/area values, respectively, compared to the UNTT design. [ABSTRACT FROM AUTHOR]

The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art. [ABSTRACT FROM AUTHOR]

This letter presents a novel and efficient hardware architecture to accelerate the computation of point multiplication (PM) primitive over arbitrary Montgomery curves (MCs). It is based on a new novel double field multiplier (DFM) that computes two field multiplications simultaneously. The DFM uses the interleaved multiplication technique, and it shortens the critical path of the circuit by computing two results at once. It is generic to work for any prime structure and curve parameters over the MCs. At the system level, a fast scheduling methodology is also presented to execute the field-level operations with the Montgomery ladder (ML) approach. Our ML and DFM designs perform the same operations regardless of the input values, which provides resistance to timing and simple power analysis side-channel attacks. It is synthesized and implemented over different FPGA platforms. The implementation results confirm that it outperforms the state-of-the-art in terms of area-time product and throughput/slice. To the best of the authors’ knowledge, it is the first fully LUT-based architecture for the arbitrary MCs. [ABSTRACT FROM AUTHOR]

Efficiently simulating solid mechanics is vital across various engineering applications. As constitutive models grow more complex and simulations scale up in size, harnessing the capabilities of modern computer architectures has become essential for achieving timely results. This paper presents advancements in running parallel simulations of solid mechanics on multi-core CPUs and GPUs using a single-code implementation. This portability is made possible by the C++ matrix and array (MATAR) library, which interfaces with the C++ Kokkos library, enabling the selection of fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. MATAR simplifies the transition from Fortran to C++ and Kokkos, making it easier to modernize legacy solid mechanics codes. We applied this approach to modernize a suite of constitutive models and to demonstrate substantial performance improvements across different computer architectures. This paper includes comparative performance studies using multi-core CPUs along with AMD and NVIDIA GPUs. Results are presented using a hypoelastic–plastic model, a crystal plasticity model, and the viscoplastic self-consistent generalized material model (VPSC-GMM). The results underscore the potential of using the MATAR library and modern computer architectures to accelerate solid mechanics simulations. [ABSTRACT FROM AUTHOR]

This paper presents software advances to easily exploit computer architectures consisting of a multi-core CPU and CPU+GPU to accelerate diverse types of high-performance computing (HPC) applications using a single code implementation. The paper describes and demonstrates the performance of the open-source C++ matrix and array (MATAR) library that uniquely offers: (1) a straightforward syntax for programming productivity, (2) usable data structures for data-oriented programming (DOP) for performance, and (3) a simple interface to the open-source C++ Kokkos library for portability and memory management across CPUs and GPUs. The portability across architectures with a single code implementation is achieved by automatically switching between diverse fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. The MATAR library solves many longstanding challenges associated with easily writing software that can run in parallel on any computer architecture. This work benefits projects seeking to write new C++ codes while also addressing the challenges of quickly making existing Fortran codes performant and portable over modern computer architectures with minimal syntactical changes from Fortran to C++. We demonstrate the feasibility of readily writing new C++ codes and modernizing existing codes with MATAR to be performant, parallel, and portable across diverse computer architectures. [ABSTRACT FROM AUTHOR]

In CPU microarchitecture, caches store frequently accessed instructions and data by exploiting their locality, reducing memory access latency and improving application performance. However, contemporary applications with large code footprints often experience frequent Icache misses, which significantly degrade performance. Although Fetch-Directed Instruction Prefetching (FDIP) has been widely adopted in commercial processors to reduce Icache misses, our analysis reveals that FDIP still suffers from Icache misses caused by branch mispredictions and late prefetch, leaving considerable opportunity for performance optimization. Priority-Directed Instruction Prefetching (PDIP) has been proposed to reduce Icache misses caused by branch mispredictions in FDIP. However, it neglects Icache misses due to late prefetch and suffers from high storage overhead. In this paper, we proposed a branch-triggered instruction prefetcher (BTIP), which aims to prefetch Icache lines that FDIP cannot efficiently handle, including the Icache misses due to branch misprediction and late prefetch. We also introduce a novel Branch Target Buffer (BTB) organization, BTIP BTB, which stores prefetch metadata and reuses information from existing BTB entries, effectively reducing storage overhead. We implemented BTIP on the Champsim simulator and evaluated BTIP in detail using traces from the 1st Instruction Prefetching Championship (IPC-1). Our evaluation shows that BTIP outperforms both FDIP and PDIP. Specifically, BTIP reduces Icache misses by 38.0% and improves performance by 5.1% compared to FDIP. Additionally, BTIP outperforms PDIP by 1.6% while using only 41.9% of the storage space required by PDIP. [ABSTRACT FROM AUTHOR]

Recent studies showed an interphase chromosome architecture—a specific coiled nucleosome structure—derived from cryopreserved EM tomograms, and dispersed throughout the nucleus. The images were computationally processed to fill in the missing wedges of data caused by incomplete tomographic tilts. The resulting structures increased z-resolution enabling an extension of the proposed architecture to that of mitotic chromosomes. Here, we provide additional insights into the chromosome architecture that was recently published [M. Elbaum et al., Proc. Natl. Acad. Sci. U.S.A. 119, e2119101119 (2022)]. We build on the defined chromosomes time-dependent structures in an effort to probe their dynamics. Variants of the coiled chromosome structures, possibly further defining specific regions, are discussed. We propose, based on generalized specific uncoiling of mitotic chromosomes in telophase, large-scale reorganization of interphase chromosomes. Chromosome territories, organized as micron-sized small patches, are constructed, satisfying complex volume considerations. Finally, we unveiled the structures of replicated coiled chromosomes, still attached to centromeres, as part of chromosome architecture. [ABSTRACT FROM AUTHOR]

Additive manufacturing (AM) technologies are unleashing the restrictions imposed by conventional manufacturing, allowing the production of innovative designs tailored to improve properties or performance. AM techniques in ceramic production allow the application of novel designs to ceramic parts, opening new opportunities for combining technologies aiming to obtain architected interpenetrating phase composites (IPCs). In this study, alumina structures with different architectures and Computer Aided Design (CAD) structure porosity oriented unidirectionally or bidirectionally, were fabricated by vat photopolymerization technique, namely Digital Light Processing. Afterwards, these structures were infiltrated with an aluminum alloy through investment casting, thus obtaining aluminum-alumina IPCs. Under compression, the IPCs presented a ductile behavior, conversely to the fragile ceramic counterparts. The IPCs compressive strength and absorbed energy were expressively higher than their ceramic counterparts. Comparing the bidirectional IPCs with the unidirectional ones, a significant increase in compressive strength and absorbed energy was observed, from 36.2% to 42.3% and from 164.8% to 358.1%, respectively, due to the greater amount and interconnection of the metal inside the ceramic structure. This study demonstrates the feasibility of this manufacturing route, combining two distinctive technologies, for the fabrication of metal-ceramic architected IPCs, allowing to tailor their mechanical properties and energy absorption capacity for a given application. [ABSTRACT FROM AUTHOR]

Measurement of a qubit (quantum bit) is a key element of quantum computation and is necessary for extracting information from a quantum processor. The physical implementation of a measurement protocol involves monitoring a physical quantity of a sensor, such as a current or a voltage, that is correlated with the state of the qubit to be measured. The monitoring of these sensors used to measure qubits in modern quantum computer architectures is typically divided between RF reflectometry and current/voltage monitoring. There are tradeoffs involved with both approaches for the reliable and accurate readout of qubits when it comes to scalable quantum computing architectures. In this article, we will review the working principles of a selection of sensors that are used to measure the state of qubits in semiconductors. The goal is to introduce electronic engineers with little or no background in quantum computing to the working principles of charge sensors in semiconductor quantum computers, their identification in various physical systems, and an overview of their design tradeoffs when measuring a qubit. This will allow electronic engineers to begin working with physics literature in the field of charge sensing. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Modern Research in English Language Studies is the property of Imam Khomeini International University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Computer vision is a growing field that uses image and video data to help machines understand the world around them. It has applications in areas like medicine, remote sensing, and manufacturing. This special issue contains nineteen scientific articles that cover a range of topics in computer vision, including target detection, facial beauty prediction, and contraband detection. The research aims to improve the accuracy and efficiency of computer vision systems in areas like autonomous driving and surveillance. However, there are challenges that developers need to address, such as algorithm efficiency, the need for labeled data, and biases in AI-based systems. [Extracted from the article]

Computer networks are by far the most popular way of transmitting information between users, despite the distance and technical and software differences. There are a large number of topologies of such networks, but the standard is client-server architecture with one server and many client machines, which will be considered and analysed in this paper. The purpose of this study is to analyse and evaluate the efficiency and speed of such a network by mathematical calculations considering such network parameters as the number of channels, the number of network nodes, the allocated space for pending requests, the frequency of requests, the average time allocated for processing one network request. The investigation and analysis of this topic will be based on analytical models created using the mathematical theory of queues applied to the principle of operation of the client-server architecture of a computer network containing only one server node. In the course of the study, the possible maximum speed of information transfer in a client-server architecture computer network with a priority of requests to a single server was mathematically calculated and considered, mathematical models were constructed, the formulas describing the dependencies of variables among themselves and their impact on the result were derived, and graphs based on them were constructed. The efficiency of the network was determined at different loads based on the data obtained. In particular, the calculation was made of the number of request packets in the network for its different loads for different percentages of the operation time of such networks. The work carried out will provide a better understanding of the methods of optimising and improving the performance of computer systems of such architecture, which will be useful in the course of their further design and physical implementation. [ABSTRACT FROM AUTHOR]

As manifestations of Industry 4.0. become visible across various applications, one key and opportune area of development are quality inspection processes and defect detection. Over the last decade, computer vision architectures, in particular, object detectors have received increasing attention from the research community, due to their localisation advantage over image classification. However, for these architectural advancements to provide tangible solutions, they must be optimised with respect to the target hardware along with the deployment environment. To this effect, this survey provides an in-depth review of the architectural progression of image classification and object detection architectures with a focus on advancements within Artificially Intelligent accelerator hardware. This will provide readers with an understanding of the present state of architecture–hardware integration within the computer vision discipline. The review also provides examples of the industrial implementation of computer vision architectures across various domains, from the detection of fabric defects to pallet racking inspection. The survey highlights the need for representative hardware-benchmarked datasets for providing better performance comparisons along with envisioning object detection as the primary domain where more research efforts would be focused over the next decade. [ABSTRACT FROM AUTHOR]

This letter focuses on the field-programmable gate array (FPGA) implementation of a Class A Middleton noise estimator, aiming to enhance its efficiency and performance. The inherent algorithm of the estimator undergoes strategic enhancements, leveraging median approximations. This endeavor leads to the development of a more streamlined and expeditious architecture. The research not only introduces the refined architecture but also conducts a comparative analysis of its attributes. The outcomes of this investigation show the benefits of algorithmic optimization, as the execution times achieved in hardware significantly surpass those attainable through software-based implementation. This underscores the practicality of the algorithmic refinement and also the notable advantages of the FPGA-based execution in terms of computational speed. [ABSTRACT FROM AUTHOR]

The Internet has become the primary vehicle for doing almost everything online, and smartphones are needed for almost everyone to live their daily lives. As a result, cybersecurity is a top priority in today's world. As Internet usage has grown exponentially with billions of users and the proliferation of Internet of Things (IoT) devices, cybersecurity has become a cat-and-mouse game between attackers and defenders. Cyberattacks on systems are commonplace, and defense mechanisms are continually updated to prevent them. Based on a literature review of cybersecurity vulnerabilities, attacks, and preventive measures, we find that cybersecurity problems are rooted in computer system architectures, operating systems, network protocols, design options, heterogeneity, complexity, evolution, open systems, open-source software vulnerabilities, user convenience, ease of Internet access, global users, advertisements, business needs, and the global market. We investigate common cybersecurity vulnerabilities and find that the bare machine computing (BMC) paradigm is a possible solution to address and eliminate their root causes at many levels. We study 22 common cyberattacks, identify their root causes, and investigate preventive mechanisms currently used to address them. We compare conventional and bare machine characteristics and evaluate the BMC paradigm and its applications with respect to these attacks. Our study finds that BMC applications are resilient to most cyberattacks, except for a few physical attacks. We also find that BMC applications have inherent security at all computer and information system levels. Further research is needed to validate the security strengths of BMC systems and applications. [ABSTRACT FROM AUTHOR]

In this article, a comprehensive review is presented of recent technological advancements utilizing electromagnetic sensors in the microwave range for detecting human vital signs and lung water levels. With the main objective of improving detection accuracy and system robustness, numerous advancements in front-end architecture, detection techniques, and system-level integration have been reported. The benefits of non-contact vital sign detection have garnered significant interest across a range of applications, including healthcare monitoring and search and rescue operations. Moreover, some integrated circuits and portable systems have lately been shown off. A comparative examination of various system architectures, baseband signal processing methods, system-level integration strategies, and possible applications are included in this article. Going forward, researchers will continue to focus on integrating radar chips to achieve compact form factors and employ advanced signal processing methods to further enhance detection accuracy. [ABSTRACT FROM AUTHOR]

Insect biodiversity and abundance are in global decline, potentially leading to a crisis with profound ecological and economic consequences. Methods and technologies to monitor insect species to aid in preservation efforts are rapidly being developed yet their adoption has been slow and focused on specific use cases. We propose a computer vision model that works towards multi-objective insect species identification in real-time and on a large scale. We leverage an image data source with 16 million instances and a recent improvement in the YOLO computer vision architecture to present a quick and open-access method to develop visual AI models to monitor insect species across climatic regions. [ABSTRACT FROM AUTHOR]

Adversarial training suffers from poor effectiveness due to the challenging optimisation of loss with hard labels. To address this issue, adversarial distillation has emerged as a potential solution, encouraging target models to mimic the output of the teachers. However, reliance on pre‐training teachers leads to additional training costs and raises concerns about the reliability of their knowledge. Furthermore, existing methods fail to consider the significant differences in unconfident samples between early and late stages, potentially resulting in robust overfitting. An adversarial defence method named Clean, Performance‐robust, and Performance‐sensitive Historical Information based Adversarial Self‐Distillation (CPr & PsHI‐ASD) is presented. Firstly, an adversarial self‐distillation replacement method based on clean, performance‐robust, and performance‐sensitive historical information is developed to eliminate pre‐training costs and enhance guidance reliability for the target model. Secondly, adversarial self‐distillation algorithms that leverage knowledge distilled from the previous iteration are introduced to facilitate the self‐distillation of adversarial knowledge and mitigate the problem of robust overfitting. Experiments are conducted to evaluate the performance of the proposed method on CIFAR‐10, CIFAR‐100, and Tiny‐ImageNet datasets. The results demonstrate that the CPr&PsHI‐ASD method is more effective than existing adversarial distillation methods in enhancing adversarial robustness and mitigating robust overfitting issues against various adversarial attacks. [ABSTRACT FROM AUTHOR]

This paper aims to propose innovative actions of advanced technological solutions and consequent necessary institutional decisions to achieve in a reasonable time the definitive confidential data protection and data sovereignty, based on available scientific results. Confidential data protection is a fundamental and strategic issue in next-generation Internet systems to guarantee data sovereignty and the respect of human rights as stated in the foundation of the United Nations. Even if presently many international regulations are decisive steps to guarantee data protection within normative contexts, they are not adequate to face new technologies, such as facial recognition, automatic profiling, position tracking, biometric data, AI applications, and many others in the future, as they are implemented without any awareness by the interested subjects. Therefore, a new approach to data protection is mandatory based on innovative and disruptive technological solutions. A recent OECD report highlighted the need for the so-called Privacy-Enhancing Technologies (PETs) for the effective protection of confidential data, even more urgent for the coexistence of privacy and data sharing in international contexts. A common feature of these technologies is the use of software methodologies that can run on currently available microprocessors and their present immaturity. More effective and definitive protection can be achieved with another methodological approach based on the paradigm of 'Data Usage Control'. This new concept guarantees data protection policy by default and initial design and it requires a new architecture of the data and a new HW&SW architecture of the computers. This contribution has a two-fold objective: first, to clarify why regulations alone and present technological proposals are not adequate for the effective and definitive protection of data and, second, to indicate the new necessary technological approach and the simultaneous institutional actions required to achieve the definitive protection and sovereignty of data in reasonable times, based on the results already available in the scientific literature. [ABSTRACT FROM AUTHOR]

The current article discusses Sierpinski networks, which are fractal networks with certain applications in computer science, physics, and chemistry. These networks are typically used in complicated frameworks, fractals, and recursive assemblages. The results derived in this study are in mathematical and graphical format for particular classes of these networks of two distinct sorts with two invariants, K-Banhatti Sombor (KBSO) and Dharwad, along with their reduced forms. These results can facilitate the formation, scalability, and introduction of novel interconnection network topologies, chemical compounds, and VLSI processor circuits. The mathematical expressions employed in this research offer modeling insights and design guidelines to computer engineers. The derived simulation results demonstrate the optimal ranges for a certain network. The optimization assistant tool deployed in this work provides a single maximized value representing the maximum optimized network. These ranges can be put into service to dynamically establish a network according to the requirements of this paper. [ABSTRACT FROM AUTHOR]

Neuromorphic devices that parallelize perception, preprocessing, and computation functions are expected to play a significant role in future non‐von Neumann architecture computers. Herein, a new retina‐inspired broadband self‐powered optoelectronic synaptic device based on 2D/3D heterojunction of epitaxial InSe on GaN(0001) is reported. Few‐layer n‐type InSe is grown on p‐type GaN by physical vapor deposition in an ultra‐high vacuum (UHV) environment. The devices are fabricated using a shadow mask assisted UHV electrode deposition technique. High‐resolution transmission electron microscopy images reveal that an atomically thin amorphous layer, which induces highly efficient charge trapping, is formed at the InSe/GaN interface. The photoresponse spans from visible to near‐infrared, and the response time is prolonged to 103 ms owing to the deep trapping levels. Thus, synaptic functions, including excitatory postsynaptic current, paired‐pulse facilitation with a high index of up to 170%, short‐term plasticity, and high‐pass filtering characteristics, are realized. Additionally, the synapses demonstrated the merit of realizing image sharpening and arithmetic operations on the same device under infrared and visible light illumination. This study provides a new platform of 2D/3D heterostructures for robust optoelectronic synapses that may find applications in post‐Moore era neuromorphic vision systems. [ABSTRACT FROM AUTHOR]

Energy distribution networks represent crucial infrastructures for modern society, and various simulation tools have been widely used by energy suppliers to manage these intricate networks. However, simulation calculations include a large number of fluid control equations, and computational overhead limits the performance of simulation software. This paper proposes a universal parallel simulation framework for energy pipeline networks that takes advantages of data parallelism and computational independence between network elements. A non-pipe model of an energy supply network is optimized, and the input and output of the network model in the proposed framework are modified, which can reduce the development burden during the numerical computations of the pipeline network and weaken the computational correlation between different simulated components. In addition, independent computations can be performed concurrently through periodic data exchange procedures between component instances, improving the parallelism and efficiency of simulation computations. Further, a parallel water pipelines network simulation computing paradigm based on a heterogeneous computer hardware architecture is used to evaluate the proposed framework's performance. A series of tests are conducted to verify the accuracy of the proposed framework, and simulation errors of less than 5% are achieved. The results of multi-threaded simulation experiments have demonstrated the feasibility of the proposed framework in a parallel computing approach. Moreover, an Advanced Micro Devices (AMD) Deep Computing Unit (DCU)-parallel program is implemented into a water supply network simulation system; the computational efficiency of this system is compared with that of its serial counterpart. The experimental results show that the proposed framework is appropriate for high-performance computer architectures, and the 18x speed-up ratio demonstrates that the parallel program based on the proposed universal framework outperforms the serial program. That provides the basis for the application of pipe network simulation on high-performance computers. [ABSTRACT FROM AUTHOR]

In today's digital landscape, organizations face significant challenges, including sensitive data leaks and the proliferation of hate speech, both of which can lead to severe consequences such as financial losses, reputational damage, and psychological impacts on employees. This work considers a comprehensive solution using a microservices architecture to monitor computer usage within organizations effectively. The approach incorporates spyware techniques to capture data from employee computers and a web application for alert management. The system detects data leaks, suspicious behaviors, and hate speech through efficient data capture and predictive modeling. Therefore, this paper presents a comparative performance analysis between Spring Boot and Quarkus, focusing on objective metrics and quantitative statistics. By utilizing recognized tools and benchmarks in the computer science community, the study provides an in-depth understanding of the performance differences between these two platforms. The implementation of Quarkus over Spring Boot demonstrated substantial improvements: memory usage was reduced by up to 80% and CPU usage by 95%, and system uptime decreased by 119%. This solution offers a robust framework for enhancing organizational security and mitigating potential threats through proactive monitoring and predictive analysis while also guiding developers and software architects in making informed technological choices. [ABSTRACT FROM AUTHOR]

Modern computer designs support composite prefetching, where multiple prefetcher components are used to target different memory access patterns. However, multiple prefetchers competing for resources can sometimes hurt performance, especially in many-core systems where cache and other resources are limited. Recent work has proposed mitigating this issue by selectively enabling and disabling prefetcher components at runtime. Formulating the problem with machine learning (ML) methods is promising, but efficient and effective solutions in terms of cost and performance are not well understood. This work studies fundamental characteristics of the composite prefetcher selection problem through the lens of ML to inform future prefetcher selection designs. We show that prefetcher decisions do not have significant temporal dependencies, that a phase-based rather than sample-based definition of ground truth yields patterns that are easier to learn, and that prefetcher selection can be formulated as a workload-agnostic problem requiring little to no training at runtime. [ABSTRACT FROM AUTHOR]

In this paper, we first analyze a real storage system consisting of 72 SSDs utilizing either Hardware RAID (HW-RAID) or Software RAID (SW-RAID), and show that SW-RAID is up to 7× faster. We then reveal that with an increasing number of SSDs, the limited I/O parallelism in SAS controllers and multi-enclosure handshaking overheads cause a significant performance drop, minimizing the total I/O Per Second (IOPS) of a 144-SSD system to less than a single SSD. Second, we disclose the most important architectural parameters that affect a large-scale storage system. Third, we propose a framework that models a large-scale storage system and estimates the system IOPS and system resource usage for various architectures. We verify our framework against a real system and show its high accuracy. Lastly, we analyze a use case of a 240-SSD system and reveal how our framework guides architects in storage system scaling. [ABSTRACT FROM AUTHOR]

GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead. [ABSTRACT FROM AUTHOR]

High-performance computing (HPC) and the cloud have evolved independently, specializing their innovations into performance or productivity. Acceleration as a Service (XaaS) is a recipe to empower both fields with a shared execution platform that provides transparent access to computing resources, regardless of the underlying cloud or HPC service provider. Bridging HPC and cloud advancements, XaaS presents a unified architecture built on performance-portable containers. Our converged model concentrates on low-overhead, high-performance communication and computing, targeting resource-intensive workloads from climate simulations to machine learning. XaaS lifts the restricted allocation model of Function as a Service (FaaS), allowing users to benefit from the flexibility and efficient resource utilization of serverless computing while supporting long-running and performance-sensitive workloads from HPC. [ABSTRACT FROM AUTHOR]

This article introduces a deniable ring signature scheme within the framework of a ring signature protocol, which allows a member of the ring to assert or deny their role as the signature's originator without the involvement of a trusted third party. Deniable ring signatures find applications in various scenarios where balancing privacy protection with supervised oversight is crucial. In this work, we present a novel deniable ring signature scheme based on the ISRSAC digital signature, tailored for environments with regulatory requirements, empowering regulators to hold malicious signers accountable. We formally validate the scheme's correctness, unforgeability, anonymity, traceability, and non-frameability through rigorous proofs. Additionally, we conduct a comparative analysis of the communication and computational overheads associated with our proposed scheme, demonstrating its superiority in practical scenarios such as electronic auctions and anonymous reporting mechanisms. [ABSTRACT FROM AUTHOR]

Emergent states are temporal group phenomena that arise from collective affective, behavioral, and cognitive processes shared among the group's members during their interactions. Cohesion is one such state, mainly conceptualized by scholars as affective in nature, and frequently distinguished into the two dimensions social and task cohesion. Whereas social cohesion is related to the need of belonging to a group, task cohesion is related to the group's goals and tasks. In this article, we emphasize the importance of behavioral interaction dynamics to predict cohesion's dynamics. Drawing from Social Science insights, we investigate the interplay between social and task cohesion to predict their dynamics across group tasks from nonverbal behavioral features. Three computational architectures exploiting transfer learning are presented. Transfer learning capitalizes on information learnt by a model for a specific dimension to predict the dynamics of the other dimension. Results show that integrating the influence of social cohesion to predict dynamics of task cohesion outperforms state-of-the-art. To predict dynamics of social cohesion, a model integrating the reciprocal impact of social and task cohesion significantly improves performance with respect to the state-of-the-art and a model only integrating the impact of task cohesion on dynamics of social cohesion. [ABSTRACT FROM AUTHOR]

Self-supervised learning has shown value for uncovering informative movement features for human activity recognition. However, there has been minimal exploration of this approach for affect recognition where availability of large labelled datasets is particularly limited. In this paper, we propose a P-STEMR (Parallel Space-Time Encoding Movement Representation) architecture with the aim of addressing this gap and specifically leveraging the higher availability of human activity recognition datasets for pain-level classification. We evaluated and analyzed the architecture using three different datasets across four sets of experiments. We found statistically significant increase in average F1 score to 0.84 for pain level classification with two classes based on the architecture compared with the use of hand-crafted features. This suggests that it is capable of learning movement representations and transferring these from activity recognition based on data captured in lab settings to classification of pain levels with messier real-world data. We further found that the efficacy of transfer between datasets can be undermined by dissimilarities in population groups due to impairments that affect movement behaviour and in motion primitives (e.g. rotation versus flexion). Future work should investigate how the effect of these differences could be minimized so that data from healthy people can be more valuable for transfer learning. [ABSTRACT FROM AUTHOR]

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Graph processing is a vital component of many AI and big data applications. However, due to its poor locality and complex data access patterns, graph processing is also a known performance killer of AI and big data applications. In this work, we propose to enhance graph processing applications by leveraging fine-grained memory access patterns with a dual-path architecture on top of existing software-based graph optimizations. We first identify that memory accesses to the offset, edge, and state array have distinct locality and impact on performance. We then introduce the Skyway architecture, which consists of two primary components: 1) a dedicated direct data path between the core and memory to transfer state array elements efficiently, and 2) a data-type aware fine-grained memory-side row buffer hardware for both the newly designed direct data path and the regular memory hierarchy data path. The proposed Skyway architecture is able to improve the overall performance by reducing the memory access interference and improving data access efficiency with a minimal overhead. We evaluate Skyway on a set of diverse algorithms using large real-world graphs. On a simulated four-core system, Skyway improves the performance by 23% on average over the best-performing graph-specialized hardware optimizations. [ABSTRACT FROM AUTHOR]

Neuromorphic computing (NC) is a crucial step toward realizing power-efficient artificial intelligence systems. Hardware implementation of NC is expected to overcome the challenges associated with the conventional von Neumann computer architecture. Synaptic devices that can emulate the rich functionalities of biological synapses are emerging. Out of several approaches, electrolyte-gated synaptic transistors have attracted enormous scientific interest owing to their similar working mechanism. Here, we report a three-terminal electrolyte-gated synaptic transistor based on Fe3O4 thin films, a half-metallic spinel ferrite. We have realized gate-controllable multilevel, non-volatile, and rewritable states for analog computing. Furthermore, we have emulated essential synaptic functions by applying electrical stimulus to the gate terminal of the synaptic device. This work provides a new candidate and a platform for spinel ferrite-based devices for future NC applications. [ABSTRACT FROM AUTHOR]