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This document specifies an interface to support the parallel features of Fortran, named the Parallel Runtime Interface for Fortran (PRIF). PRIF is a proposed solution in which the runtime library is responsible for coarray allocation, deallocation and accesses, image synchronization, atomic operations, events, and teams. In this interface, the compiler is responsible for transforming the invocation of Fortran-level parallel features into procedure calls to the necessary PRIF procedures. The interface is designed for portability across shared- and distributed-memory machines, different operating systems, and multiple architectures. Implementations of this interface are intended as an augmentation for the compiler's own runtime library. With an implementation-agnostic interface, alternative parallel runtime libraries may be developed that support the same interface. One benefit of this approach is the ability to vary the communication substrate. A central aim of this document is to define a parallel runtime interface in standard Fortran syntax, which enables us to leverage Fortran to succinctly express various properties of the procedure interfaces, including argument attributes.

We address the challenges of scaling verification efforts to match the increasing complexity and size of systems. We propose a research agenda aimed at building a performant proof engine by studying the asymptotic performance of proof engines and redesigning their building blocks. As a case study, we explore equational rewriting and introduce a novel prototype proof engine building block for rewriting in Coq, utilizing proof by reflection for enhanced performance. Our prototype implementation can significantly improve the development of verified compilers, as demonstrated in a case study with the Fiat Cryptography toolchain. The resulting extracted command-line compiler is about 1000 × faster while featuring simpler compiler-specific proofs. This work lays some foundation for scaling verification efforts and contributes to the broader goal of developing a proof engine with good asymptotic performance, ultimately aimed at enabling the verification of larger and more complex systems. [ABSTRACT FROM AUTHOR]

Formally verified compilers and formally verified static analyzers are a solution to the problem that certain industries face when they have to demonstrate to authorities that the object code they run truly corresponds to its source code and that it satisfies certain properties. From a scientific and technological point of view, they are a challenge: not only a number of nontrivial invariants and algorithms must be proved to be correct, but also the implementation must be reasonably effective so that the tools operate within reasonable time. Many optimizations in compilers rely on static analysis, and thus a formally verified compiler entails formally verified static analyses. In this paper, we explain some difficulties, possible solutions, design choices, and trade-offs pertaining to verified static analysis, in particular, when the solution of the analysis is expressed as some form of tree, map, or set. [ABSTRACT FROM AUTHOR]

The adjoint method provides an efficient way to compute sensitivities for system models with a large number of inputs. However, implementing the adjoint method requires significant effort that limits its use. The effort is exacerbated in large-scale multidisciplinary design optimization. We propose the adoption of a three-stage compiler as the method for constructing computational models for large-scale multidisciplinary design optimization to enable accurate and efficient adjoint sensitivity analysis. We develop a new modeling language called the Computational System Design Language that provides an appropriate input to the compiler front end that works well with multidisciplinary models. This paper describes the three-stage compiler methodology and the Computational System Design Language. The proposed solution uses a graph representation of the numerical model to automatically generate a computational model that computes adjoint-based sensitivities for use within an optimization framework. For two engineering models, this approach reduces the amount of user code by a factor of approximately two compared to their original implementations, without a measurable increase in computation time. This paper also includes a best-case complexity analysis that is built into the compiler implementation to allow users to estimate the memory required to evaluate a computational model and its derivatives, which is independent of the compiler back end that ultimately generates the computational model. Future compiler implementations are expected to approach the theoretical best-case memory cost and improve run time performance for both model evaluation and derivative computation. [ABSTRACT FROM AUTHOR]

Non-control-data attacks are those attacks that purely target and modify the non-control data of a program, such as boolean values, user input or configuration parameters, and leave the control flow of a program untouched. These attacks were considered a niche due to the high difficulty in crafting attacks that do not modify the control flow. However, in recent years researchers have already demonstrated that non-control-data attacks can be automatically constructed and that they pose a significant threat because they can compromise critical and widely used software, such as web browsers and the Linux kernel. Moreover, they can also be used to disable or bypass state-of-the-art software security techniques, such as control-flow integrity. The most promising technique to protect against non-control-data attacks is data-flow integrity, however, modern compilers do not implement this protection yet. In this work we present an optimized data-flow integrity implementation for modern compilers that reduces the amount of basic blocks that need to be protected in an average of 45.8%, it also has broader security guarantees due to its more precise static analysis. Finally, we evaluate the completeness of our optimized data-flow integrity implementation.

Large language models (LLMs) have been massively applied to many tasks, often surpassing state-of-the-art approaches. While their effectiveness in code generation has been extensively studied (e.g., AlphaCode), their potential for code detection remains unexplored. This work presents the first analysis of code detection using LLMs. Our study examines essential kernels, including matrix multiplication, convolution, fast-fourier transform and LU factorization, implemented in C/C++. We propose both a preliminary, naive prompt and a novel prompting strategy for code detection. Results reveal that conventional prompting achieves great precision but poor accuracy (67.5%, 22.5%, 79.5% and 64% for GEMM, convolution, FFT and LU factorization, respectively) due to a high number of false positives. Our novel prompting strategy substantially reduces false positives, resulting in excellent overall accuracy (91.2%, 98%, 99.7% and 99.7%, respectively). These results pose a considerable challenge to existing state-of-the-art code detection methods.

FPGA accelerators offer performance and efficiency gains by narrowing the scope of acceleration to one algorithmic domain. However, real-life applications are often not limited to a single domain, which naturally makes Cross-Domain Multi-Acceleration a crucial next step. The challenge is, existing FPGA accelerators are built upon their specific vertically-specialized stacks, which prevents utilizing multiple accelerators from different domains. To that end, we propose a pair of dual abstractions, called Yin-Yang, which work in tandem and enable programmers to develop cross-domain applications using multiple accelerators on a FPGA. The Yin abstraction enables cross-domain algorithmic specification, while the Yang abstraction captures the accelerator capabilities. We also develop a dataflow virtual machine, dubbed XLVM, that transparently maps domain functions (Yin) to best-fit accelerator capabilities (Yang). With six real-world cross-domain applications, our evaluations show that Yin-Yang unlocks 29.4× speedup, while the best single-domain acceleration achieves 12.0×.

С ростом популярности модульной парадигмы программирования количество косвенных переходов в продуцируемом коде значительно возросло. Аппаратные способы уменьшить задержки, связанные с такими переходами, требуют сложной логики непосредственно на кристалле, которую зачастую невыгодно реализовывать из-за дополнительного энергопотребления процессора. Существующие в компиляторе GCC-подходы преобразования косвенных переходов позволяют существенно увеличить производительность программ, однако без сбора статистики и перекомпиляции кода все еще остается большое количество непреобразованных переходов, которые приводят к уменьшению производительности программ. В этой статьи предлагается два метода повышения производительности, связанных с оптимизацией косвенных переходов. Статический метод позволяет расширить существующие оптимизационные возможности компилятора. Динамический метод является новым подходом подстановки целевых адресов переходов во время выполнения программы. Наше исследование показывает, что эти подходы способны увеличить производительность отдельных участков программ, содержащих косвенные переходы, до 2,3 раза. Применение статического метода позволило улучшить производительность отдельных тестов из пакета CPUBench на 15 % при увеличении затраченного на компиляцию времени не более чем на 1 %.

We introduce isQ, a new software stack for quantum programming in an imperative programming language, also named isQ. The aim of isQ is to make programmers write quantum programs as conveniently as possible. In particular, 1) the isQ language and its compiler contain many useful features, including but not limited to classical control flow, such as recursion, decomposition of self-defined unitary gates, and oracle programming and its circuit realization. 2) To make it flexible, an isQ program can be compiled into several different kinds of intermediate representation and assemblies, including QIR, eQASM, OpenQASM 3.0, and QCIS (specially tailored for the superconducting quantum hardware at the University of Science and Technology of China). 3) Besides interfacing isQ with real superconducting hardware, a QIR simulator is also developed for the demonstration and testing of isQ programs. The isQ software stack encompasses abundant compiler optimizations of high-level quantum programs. To realize it, a distinct multilevel intermediate representation (MLIR) dialect name isQ-IR is proposed.

It is difficult to imagine modern information systems without the use of multithreading. The use of multithreading can both improve the performance of the system as in whole so as slow down the execution of multithreaded applications due to the occurrence of multithreaded programming errors. To find such errors in C/C++ languages, there exists a Google Thread Sanitizer compiler module. The order of execution of threads can change every time the program is started for execution and can affect the appearance of such errors. To repeatedly change the order of execution of threads during the execution of the program, Google Thread Sanitizer has a fuzzing testing module that allows you to increase the probability of finding errors. But all the thread scheduling algorithms in this module are presented in the form of sequential execution of threads which can lead to a significant slowdown in Google Thread Sanitizer as well as can affect the testing of applications that depends on timers (waiting for network events, deadline for operations, ...). To speed up the work of fuzzing schedulers, a method for parallelizing independent transitions is proposed. From the point of view of multithreaded programming errors, it is only important to change the shared state between threads, and local calculations do not affect the reproduction of multithreaded errors. The changes of shared states themselves occur at synchronization points (places in the code where threads are switched according to the principle of cooperative multitasking). The method suggests ordering only the change of shared states at synchronization points, and performing local calculations in parallel, due to which parallelization is achieved. For the analysis of theoretical complexity of the algorithm, the method of combinatorial counting is used. A new approach to the organization of fuzzing testing based on the method of parallelization of independent transitions is proposed the implementation of which, according to theoretical and practical estimates, shows a noticeable acceleration of the work of fuzzing schedulers. According to the results of the experiment, it was revealed that for the algorithm of iterating through all execution variants, the acceleration of execution reaches 1.25 times for two threads. For an arbitrary number of threads, an estimate is presented in the form of a formula. The proposed approach allows fuzzing tests to cover multithreaded applications for which execution time is important — applications with reference to timers which improve the quality of the software.

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Computations on video cards and specialized accelerators are widely used to solve many important practical tasks. Developers working with OpenCL, SYCL, CM, and ISPC rely heavily on the quality of optimizations in graphics compilers. For the Intel GPU, the compiler has two parts: a scalar part that works in the SIMT model, and a vector part that targets SIMD languages. It is the vector part of the compiler that contributes the most when it comes to critical tasks such as training neural networks, solving systems of equations, rendering images, and so on. Unfortunately, until recently, the Intel graphics compiler architecture lacked the ability to properly decompose into vector registers, which led to particular performance problems in programs written in ISPC, such as Embree and OSPRay. To solve this problem, we propose a structure partitioning algorithm for the vector optimizer of the Intel graphics compiler. A detailed description of the algorithm and performance measurements are given, showing an increase of up to 80% on some tasks.

Control flow optimizations are of particular importance when optimizing programs for graphics accelerators and video cards. In addition to scalar control flow optimizations, which are widely known and well represented in modern compilers, there is also a current issue of vector control flow optimizations. On the one hand, vector control flow is natural for high-level languages such as ISPC and CM, where vector control constructs are part of the semantics of ordinary programs. On the other hand, vector primitives, including those for vector control flow, are present in modern graphics accelerators, such as Intel XE. Support in the hardware can significantly improve the performance of programs. In this case, the main problem is the lack of vector control structures in a stable intermediate representation. This paper proposes an intermediate scalar representation for vector control structures through explicit predicates and an algorithm for restoring the vector control flow from this representation in a graphical optimizer.

Scattering problems have been evaluated and studied to reach to new solution methods by researchers. In this paper, the scattering calculation analysis in multi-frequency band is presented for the homogenous and the inhomogeneous 2D and 3D structures by the Shifted Frequency Internal Equivalence (SFIE). This paper is also a collection of the previous studies in one place, the interrelation of results on SFIE to enlighten the researchers on the subject matter for further research areas. This theory has shown that the electromagnetic field at frequency ω inside the region can be solved by using a set of equivalent currents radiating at the different frequency ω0. This chosen ω0 frequency is not changed while the incident field frequency changes. The analysis method in the literature requires repetition of the numerical analysis as many times as the number of the related frequency. Each repetition adds up to the computer time. SFIE algorithm which solves Electric and Magnetic Field Integral Equations (EFIE and MFIE) defines current equivalency covering the dielectric-magnetic features of the structure. SFIE applications are proved to give successful results for 2D and 3D arbitrary geometries. SFIE also provides very successful results for lossy objects. [ABSTRACT FROM AUTHOR]

Modern compilers can be useful, not only in detecting programming errors but also by suggesting several repairs and solutions for those errors using error repair techniques. Error repair refers to the process of finding a repair for an error that happens as a result of compiling a piece of code written by computer programmers. However, a repair is not always consistent with the purpose of programmers. This means a compiler suggests a repair which is different from what the programmer wanted to write. Many compilers fail to suggest the correct repair when programming errors occur as a result of misspelling errors. The aim of this paper is to enhance the error repair process in compilers using spelling correction algorithms. A typical compiler does not provide solutions for the most common syntax programming errors which occur as a result of misspelling. Such errors are easy to detect by compilers but difficult to suggest a fix that is the correct form. Therefore, a novel error correction mechanism which is called CoEdit approach is developed to help compilers to suggest the most suitable repair for programming errors occurred as a result of mistyping errors. Four-Way and Editex algorithms are well known spelling correction algorithms are also extended and employed to be compatible to work with programming languages. CoEdit approach employs these algorithms in order to find repairs to misspelling errors. CoEdit is a generic approach to enhance error repair in any compilers for any language because it targets misspelling compiler errors. This paper concludes that using the Editex algorithm with CoEdit is the best choice in the case of finding repairs to programming errors that occur as a result of spelling errors. [ABSTRACT FROM AUTHOR]

Recent refactoring of the GPUSPH codebase have uncovered some of the limitations of the official CUDA compiler (nvcc) offered by NVIDIA when dealing with some C++ constructs, which has shed some new light on the relative importance of the neighbors list construction and traversal in SPH codes, presenting new possibility of optimization with surprising performance gains. We present our solution for high-performance neighbors list construction and traversal, and show that a 4 × speedup can be achieved in industrial applications. • Neighbors list construction and traversal performance has a significant impact in SPH. • Using different compilers can help identify missed optimization opportunities. • Particle-centric may not be the most efficient parallelization for SPH on GPU. • Large single-GPU speed-ups can negatively affect multi-GPU scaling. [ABSTRACT FROM AUTHOR]

With the undeniable increase in popularity of open source software, also the availability and reuse of source code have increased. While the detection of code clones helps tracking reuse and evolution while dealing with source code, little prior work exists that can be used in binary code. This is complicated by the increased difficulty posed by the compilation transformations. In this paper, we present a CFG refinement useful to find function-level clones in a fast and scalable way by comparing the high-level structure of multiple disassembled binaries altogether. We are capable of determining if functions belonging to other programs have been copied or reused, even when the processor architecture is different. Specifically, our algorithm consists in the extraction of the various functions flows and the reconstruction of a higher level structure, leveraging architectural differences and allowing efficient comparison in linear time with structural hashing. We implemented our idea in a tool called BinCC, and analyzed 24 million functions spanning different architectures and optimization levels. Results show that our approach can achieve precision between 91% and 99% within the same architecture and 75% in detecting clones among different architectures, and can also detect the presence of specific library functions inside an executable. Our approach can reach comparable precision of current state-of-the-art learning approaches while being three order of magnitude faster.

The correctness of debug information included in optimized binaries has been the subject of recent attention by the research community. Indeed, it represents a practically important problem, as most of the software running in production is produced by an optimizing compiler. Current solutions rely on invariants, human-defined rules that embed the desired behavior, whose violation may indicate the presence of a bug. Although this approach proved to be effective in discovering several bugs, it is unable to identify bugs that do not trigger invariants. In this paper, we investigate the feasibility of using Deep Neural Networks (DNNs) to discover incorrect debug information. We trained a set of different models borrowed from the NLP community in an unsupervised way on a large dataset of debug traces and tested their performance on two novel datasets that we propose. Our results are positive and show that DNNs are capable of discovering bugs in both synthetic and real datasets. More interestingly, we performed a live analysis of our models by using them as bug detectors in a fuzzing system. We show that they were able to report 12 unknown bugs in the latest version of the widely used LLVM toolchain, 2 of which have been confirmed.

We observe a disconnect between developers and end-users of linear algebra libraries. On the one hand, developers invest significant effort in creating sophisticated numerical kernels. On the other hand, end-users are progressively less likely to go through the time consuming process of directly using said kernels; instead, languages and libraries, which offer a higher level of abstraction, are becoming increasingly popular. These languages offer mechanisms that internally map the input program to lower level kernels. Unfortunately, our experience suggests that, in terms of performance, this translation is typically suboptimal. In this paper, we define the problem of mapping a linear algebra expression to a set of available building blocks as the "Linear Algebra Mapping Problem" (LAMP); we discuss its NP-complete nature, and investigate how effectively a benchmark of test problems is solved by popular high-level programming languages and libraries. Specifically, we consider Matlab, Octave, Julia, R, Armadillo (C++), Eigen (C++), and NumPy (Python); the benchmark is meant to test both compiler optimizations, as well as linear algebra specific optimizations, such as the optimal parenthesization of matrix products. The aim of this study is to facilitate the development of languages and libraries that support linear algebra computations. [ABSTRACT FROM AUTHOR]

Field-programmable gate array (FPGA) accelerators offer performance and efficiency gains by narrowing the scope of acceleration to one algorithmic domain. However, real-life applications are often not limited to a single domain, which naturally makes Cross-Domain Multi-Acceleration a crucial next step. The challenge is, existing FPGA accelerators are built upon their specific vertically specialized stacks, which prevents utilizing multiple accelerators from different domains. To that end, we propose a pair of dual abstractions, called Yin-Yang, which work in tandem and enable programmers to develop cross-domain applications using multiple accelerators on a FPGA. The Yin abstraction enables cross-domain algorithmic specification, while the Yang abstraction captures the accelerator capabilities. We also developed a dataflow virtual machine, dubbed Accelerator-Level Virtual Machine (XLVM), which transparently maps domain functions (Yin) to best-fit accelerator capabilities (Yang). With six real-world cross-domain applications, our evaluations show that Yin-Yang unlocks 29.4× speedup, while the best single-domain acceleration achieves 12.0×. [ABSTRACT FROM AUTHOR]

This article discusses the problem of automatic generation of peephole-optimization of the static bytecode optimizer of a virtual machine (VM) concerning the task of improving the instruction set architecture (ISA) of the VM. Peephole optimization is one of the stages of the optimizing compiler. It applies to the code of the original input program in an intermediate representation (IR or LLIR) and resides in finding sequences of instructions that match known templates and replacing them with shorter or faster semantically equivalent sequences. The current peephole optimization approaches assume some limited set of templates or functions that are manually encoded while relying on the engineers' in-depth knowledge of the corresponding IR and the structure of the compiler output programs. Also, for various IRs you must re-encode similar peephole optimizations, which entails additional monetary and time costs. An alternative approach is superoptimization, which consists of the automatic generation of templates and their matching rules. Among the main parts of the superoptimizer there are the search algorithm, the cost function, and the equivalence verifier. In the article algorithm for solving a more specialized subtask was implemented and tested. It consists in finding and counting the most frequent instruction templates, which can later be replaced with one new instruction to optimize execution time and/or bytecode size or be analyzed by a programmer to investigate the weaknesses of the existing ISA and obtain information about the specifics of the source data.

Coexistence of software components and functions of different criticality in a single computing platform has challenged the safety community for the past two decades. Despite efforts that have been made so far, dealing with mixed-criticality has still left some room for improvements. One particular concern here is that partitioning of hardware and software resources with regard to criticality (safety related, non-safety related) has direct implications on how safety measures need to be realised. For example, a self-test that must meet certain diagnostic coverage for the microcontroller core by inspecting its instructions, needs to cover only those instructions which are able to affect a safety function. Available software mechanisms and tools are to a certain extent still unable to deal with such a fine-grained selection of resources. In this work, we introduce a compiler extension and language support which enable accurate selection of data based on their criticality. The compiler extension serves to establish detailed traceability between the software code and its representation in runtime memory. With the language support, the individual data elements can be classified based on the desired safety integrity level. As a result, safety measures that operate on data (e.g. Abraham test for SRAM can achieve better coverage. The method has been evaluated and applied to industrial safety controllers. We provide here relevant performance figures and discuss possible applications of the method in other fields.

Dataflow is a parallel and generic model of computation that is agnostic of the underlying multi/many-core architecture executing it. State-of-the-art frameworks allow fast development of dataflow applications providing memory, communicating, and computing optimizations by design time exploration. However, the frameworks usually do not consider cache memory behavior when generating code. A generally accepted idea is that bigger and multi-level caches improve the performance of applications. This work evaluates such a hypothesis in a broad experiment campaign adopting different multi-core configurations related to the number of cores and cache parameters (size, sharing, controllers). The results show that bigger is not always better, and the foreseen future of more cores and bigger caches do not guarantee software-free better performance for dataflow applications. Additionally, this work investigates the adoption of two memory management strategies for dataflow applications: Copy-on-Write (CoW) and Non-Temporal Memory transfers (NTM). Experimental results addressing state-of-the-art applications show that NTM and CoW can contribute to reduce the execution time to -5.3% and - 15.8 % , respectively. CoW, specifically, shows improvements up to -21.8% in energy consumption with -16.8% of average among 22 different cache configurations. [ABSTRACT FROM AUTHOR]

While compiling a native application, different compiler flags or optimization levels can be configured. This choice depends on the different requirements. For example, if the application binary is intended for final release, the flags and optimization settings should be set for execution speed and efficiency. Alternatively, if the application is to be used for debugging purposes, debug flags should be configured accordingly, usually involving minor or no code optimization. However, this information cannot be easily extracted from a compiled binary. Nonetheless, ensuring the same compiler and compilation flags is particularly important when comparing different binary files, to avoid inaccurate or unreliable analyses. Unfortunately, to understand which flags and optimizations have been used, a deep knowledge of the target architecture and the compiler used is required. In this study, we present two deep learning models used to detect both compiler and optimization level in a compiled binary. The optimization levels we study are O0, O1, O2, O3, and Os in the x86_64, AArch64, RISC-V, SPARC, PowerPC, MIPS, and ARM architectures. In addition, for the x86_64 and AArch64 architectures, we also determine whether the compiler is GCC or Clang. We created a dataset of more than 76000 binaries and used it for training. Our experiments showed over 99.95% accuracy in detecting the compiler and between 92% to 98%, depending on the architecture, in detecting the optimization level. Furthermore, we analyzed the change in accuracy when the amount of data was extremely limited. Our study shows that it is possible to accurately detect both compiler flag settings and optimization levels with function-level granularity.

We present a simple compilation strategy for safety-checking array indexing in high-level languages on GPUs. Our technique does not depend on hardware support for abnormal termination, and is designed to be efficient in the non-failing case. We rely on certain properties of array languages, namely the absence of arbitrary cross-thread communication, to ensure well-defined execution in the presence of failures. We have implemented our technique in the compiler for the functional array language Futhark, and an empirical evaluation on 19 benchmarks shows that the geometric mean overhead of checking array indexes is respectively 4% and 6% on two different GPUs. [ABSTRACT FROM AUTHOR]