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This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. [ABSTRACT FROM AUTHOR]

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 Vpp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature. [ABSTRACT FROM AUTHOR]

This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA's linearity can be improved. The PGA's linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc. [ABSTRACT FROM AUTHOR]

An improved class AB version of the super source follower is used to implement a compact and power-efficient second order analog low-pass filter. The proposed circuit achieves a 41% power reduction as well as an improvement in linearity and pass band gain with respect to its class A counterpart. Measurement results of a test chip prototype fabricated in a 180 nm CMOS technology show a power consumption ranging from 50.3 $\mu \text{W}$ to 85.27 $\mu \text{W}$ for cutoff frequencies from 600 kHz to 890 kHz, with a supply voltage of ±0.75 V. A third order intermodulation distortion of −35.34 dB (for an input signal of 0.4 mVpp and 350 kHz) and a THD of −69.7 dB (for an input signal of 0.4 mVpp and 100 kHz) are measured, which results in an improvement with respect to the conventional class A version of 13.98 dB and 43.6 dB, respectively. The silicon area is 0.0592 mm2 (using external capacitors). [ABSTRACT FROM AUTHOR]

This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA’s linearity can be improved. The PGA’s linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc.

Class AB audio amplifiers are commonly used but the efficiency is 50%. While the efficiency of class D audio amplifiers is 90% but are rarely used. The purpose of this research is to know how much the power efficiency of field sound system between 1000 watts class AB amplifier and 900 watts class D amplifier. This study is a comparative study that compares different variables with the same sample. The results of power efficiency are obtained from the percentage comparison between the output power and the input power of each audio amplifier. The power efficiency of class D audio amplifiers with IRS D900 type larger than class AB audio amplifiers with Apex B500 type. The efficiency value of class D audio amplifiers at the highest output power reaches 87% while class AB audio amplifiers are only 73%.

In this paper, a novel current output stage (COS) is introduced. Deliberately compose of class AB operation and a special voltage sense and current compensation scheme enables the structure to operate at extreme voltage beyond the triode limits to achieve wide voltage dynamic range and grants it such following ever demanded merits at power supplies of 1.8V: low power consumption of 40 µW, high drive to bias current ratio of 100. The results are verified by Spectre post-layout simulation using 0.18 µm CMOS standard technology of TSMC. The process, the stability and robustness of the proposed COS are verified by stepwise response and Monte Carlo and corner simulations, respectively. [ABSTRACT FROM AUTHOR]

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 10.6 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath G m - C compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65 nm 1.2 V CMOS process, achieving 808 MHz gain-bandwidth, 119 dB DC gain, 585 V/ μ s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2 V with power consumption of 2.17 mW and the layout area is 0.011 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we analyze energy-efficient communications based on an advanced energy consumption model for wireless devices. The developed model captures relationships between transmission power, transceiver distance, modulation order, channel fading, power amplifier (PA) effects, as well as other circuit components in the radio frequency transceiver. Based the developed model, we are able to identify the optimal modulation order in terms of energy-efficiency under different situations (e.g., different transceiver distance, different PA classes and efficiencies, different pulse shape, etc). This provides an important framework for analyzing energy-efficient communications for different wireless systems ranging from cellular networks to wireless Internet of Things. [ABSTRACT FROM AUTHOR]

New techniques for controlling the gain of a programmable gain amplifier (PGA) using an eight-bit digital word has been proposed in this paper. The output taps of the R–2R ladder network feed just the two Gm stages through the switches controlled by three MSB bits of the control word. The parasitic capacitance at the different taps has been reduced and equalized making the bandwidth of the PGA wider and the gain error more uniform over the entire control span. Two current banks composed of 32 current sources plus a 10 µA dummy current source, controlled by the five LSB bits of the digital control word, determine the tail currents of the Gm stages to set the PGA gain precisely linear in dB. Dummy current sources, however, have no effect on the gain of the PGA, they will prevent the transistors from turning OFF making the gain update rate faster. A differential PGA has been designed in a 0.18 µm–1.8 V-CMOS technology. The maximum gain error is less than 0.03 dB in different corner cases. At the maximum gain, the bandwidth and the input referred noise voltage of the PGA are 82 MHz and 4.1 nV/√Hz respectively, while the circuit draws just 4.8 mA current from the supply. [ABSTRACT FROM AUTHOR]

Summary: A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application. [ABSTRACT FROM AUTHOR]

This brief presents the experimental validation of a low-power, large output swing, class-AB buffer amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed buffer amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$) is found. [ABSTRACT FROM AUTHOR]

This paper presents a class-AB amplifier with enhanced transconductance and slew rate using adaptive biasing technique and new drivers. The adaptive biasing configuration provides a tail current linked to the input signal in order to increase the slew rate during slewing phase. In addition, the new structure benefits from new drivers to enhance the transconductance which are supported by adaptive biasing configuration. These enhancement techniques lead to the input and output class-AB operations for fast settling applications. The proposed structure is simulated in 65-nm complementary metal-oxide semiconductortechnology which shows a 16.2-dB enhancement in the DC gain and a 72% reduction in the settling time compared to the conventional structure. [ABSTRACT FROM AUTHOR]

A scheme to achieve simultaneously extremely high slew-rate improvement and avoiding open-loop gain degradation in one-stage super class AB op-amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high-output current enhancement factors at the expense of degrading the open-loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew-rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180-nm complementary metal-oxide semiconductor technology with open-loop gain of 67 dB, a factor 2 improvement in GBW, and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A programmable gain amplifier (PGA) is presented, targeting amplifying input signal with high dynamic range and low noise. The proposed PGA adopts fully balanced differential difference amplifier (FBDDA) as main amplifier. A class-AB implementation of output stage is advantageous in order to achieve high current driving capability with very low quiescent power consumption. Combining resistor-feedback loop controlled by digital signal, the proposed PGA achieves a dB-linear gain range from 0 to 15 dB with a gain step of 1 dB. Compared with previous works, the theoretical analysis and measurement results prove that the proposed structure has lower noise. The circuit was designed and fabricated in SMIC 0.18 µm 3.3 V process, showing a gain error of less than 0.25 dB, a third harmonic distortion (HD3) of better than −83 dB and a thermal noise of 1.6 nv / Hz . The measurement results indicate that the PGA described here has a −3 dB bandwidth of 387.5 MHz at maximum gain of 15 dB. The PGA occupies a chip area of 0.1 mm 2 . [ABSTRACT FROM AUTHOR]

In this paper we extend the figures of merit for class AB symmetrical OTAs to the fully differential case and compare topologies from the literature. This analysis shows that the power consumption of the CMFB can have a significant role in determining the efficiency of the OTA, but on the other hand a CMFB is needed both to set the desired output common mode voltage and to improve the CMRR. We propose the complementary triode CMFB, i.e. a triode CMFB applied both at the NMOS and PMOS current mirrors, as suitable for class AB symmetrical OTAs, and show some case studies in deep submicron CMOS technology to assess the effectiveness of the proposed solution. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper a high speed class AB switched-current memory cell is presented. Memory transistors have been designed in triode region in order to reduce the threshold voltage mismatch and clock feed-through errors. Also a modified Flipped Voltage Follower (FVF) circuit is used to cancel charge injection error. Besides, this cell consists of a new common-mode feedforward (CMFF) circuit which attenuates the common mode components and improves offset error at output. Furthermore, a coupled differential (CDR) memory cell (MC) is used to eliminate the clock feedthrough (CFT) error considerably. All of the presented circuits have been designed by using TSMC 0.18 μm process parameters and simulated in HSPICE. Simulation results show that maximums of THD, SNR and SFDR at clock frequency of 100 MHz and 1 MHz as input frequency are –71 dB, 71.2 dB and 68 dB respectively. Obtained results demonstrated considerable improvement in the circuit performance which confirm the excellence of proposed memory cell in comparisons to previous cells. [ABSTRACT FROM AUTHOR]

An 82 mW fully integrated stereo ground-referenced headphone module is designed in 40 nm CMOS. Lower platform cost is enabled by integrating the headphone module on the same SoC as the baseband functions. Maintaining device reliability with direct battery hook-up and providing large output swing are major challenges for this work, and several techniques were employed to guarantee safe operation for all of the devices under various conditions. Area reduction techniques were utilized to reduce the die cost and achieve lower platform cost. The module supports direct battery hookup with a battery range from 3.1 to 4.5 V and achieves a minimum low frequency, i.e., 217 Hz, PSRR of 110 dB at the lowest battery voltage. Audio quality is preserved by achieving a dynamic range of 100 dB, THD+N of -84 dB at 10 mW output power, and 160 \muV pop-and-click noise level during power-up and power-down. The module occupies an area of 0.675 mm^2 on the SoC. [ABSTRACT FROM AUTHOR]

A true class 'AB' fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 μm CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of ±0.9 V. The interesting results such as current drive capability of ±100 μA, high output voltage swing of ±0.8 V, low static power consumption of 21 μW, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit's linearity. The transient stepwise response analysis is also done to verify the stability of proposed class 'AB' FDCOS. [ABSTRACT FROM AUTHOR]

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm^2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours. [ABSTRACT FROM AUTHOR]

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm^2, and at 6-dB back-off power, the PAE is 21%. [ABSTRACT FROM AUTHOR]

A novel class-AB variable gain amplifier with constant bandwidth and continuous gain tuning is presented. It is based on the cascade connection of a tunable transconductor and a transresistance amplifier. Class-AB operation is achieved using quasi-floating gate transistors. The circuit has been fabricated in a 0.5- \mu\m CMOS technology, showing a third-order input intercept point (IIP3) of 13 dBVp for a power consumption of 500 \mu\W. [ABSTRACT FROM AUTHOR]

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance ( G), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5 μw. G variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is −46 dB for 2.15 v differential output voltage signal with applying a 0.48 v input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process. [ABSTRACT FROM AUTHOR]

Two prior-art transconductance amplifier-based rail-to-rail class-AB analog buffers are examined. Their analysis reveals that the output current drive capability for large input voltages is restricted. To mitigate this drawback, a relatively simple slew-rate enhancement scheme is proposed. The new scheme allows the buffer's speed to be increased by over 200% with only a very small increase in static power consumption (1.25%) and silicon area (3%). The proposed and the two conventional buffers were fabricated in a 0.35-\mu \m CMOS technology for a power supply of 3 V. Measurements verify the superior slew-rate performance of the new buffer for rail-to-rail step responses. [ABSTRACT FROM AUTHOR]

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29dBm and a power-added efficiency of 24% with a power gain of 20dB, including the losses of the bond-wires. [Copyright &y& Elsevier]

Three representative class AB Current Mirror OTAs are analytically compared in term of the tradeoffs among speed, current consumption and area. The approach presented allows to derive useful design guidelines. The analysis was validated by means of simulations in a 90 nm CMOS technology. [ABSTRACT FROM AUTHOR]