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In this paper, a novel locally active memristor is constructed. Based on the 3D Hindmarsh–Rose (HR) and 2D FitzHugh–Nagumo (FHN) neuron, a heterogeneous neuronal system is constructed by connecting the two neurons with the locally active memristor. The equilibrium point and stability of the system are investigated. The dynamic behavior of the system is numerically and experimentally revealed by utilizing dynamic analyses in terms of interspike interval bifurcation diagram, two-parameter bifurcation diagram and so on. The unique and abundant dynamic behavior is found in the proposed neuronal system by varying the coupling strength, external stimulus current, memristive parameter and other system parameters. Multiple bursting firing groups in the tongue-shaped domains have been discovered for the first time. Finally, in order to validate the numerical simulation, an analog equivalent circuit of the heterogeneous neuronal system is devised, which demonstrates that the system is physically realizable. [ABSTRACT FROM AUTHOR]

Abstract In this paper, we introduce a category of Novel Jerk Chaotic (NJC) oscillators featuring symmetrical attractors. The proposed jerk chaotic system has three equilibrium points. We show that these equilibrium points are saddle-foci points and unstable. We have used traditional methods such as bifurcation diagrams, phase portraits, and Lyapunov exponents to analyze the dynamic properties of the proposed novel jerk chaotic system. Moreover, simulation results using Multisim, based on an appropriate electronic implementation, align with the theoretical investigations. Additionally, the NJC system is solved numerically using the Dormand Prince algorithm. Subsequently, the Jerk Chaotic System is modeled using a multilayer Feed-Forward Neural Network (FFNN), leveraging its nonlinear mapping capability. This involved utilizing 20,000 values of x 1, x 2, and x 3 for training (70%), validation (15%), and testing (15%) processes, with the target values being their iterative values. Various network structures were experimented with, and the most suitable structure was identified. Lastly, a chaos-based image encryption algorithm is introduced, incorporating scrambling technique derived from a dynamic DNA coding and an improved Hilbert curve. Experimental simulations confirm the algorithm’s efficacy in enduring numerous attacks, guaranteeing strong resiliency and robustness.

In the Fourier triangular basis neural network model, the calculation of weights based on BP iterative algorithm has a longer training time. To improve this situation, a Fourier neural network circuit design based on direct weight method is proposed in this paper, which can realize the fast calculation of neural network weights in one step. Moreover, the circuit can realize the dynamic fitting of different curves by adjusting the memristors. Some functions are given as examples to verify the accuracy, error and prediction ability of the fitting. The PSPICE simulation results demonstrate that the average accuracy rate achieves 96.21%. Compared with the BP algorithm on MATLAB, the operation speed of this circuit is improved by several orders of magnitude and has better function prediction ability. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs. [ABSTRACT FROM AUTHOR]

The paper reports simple yet effective circuits for realizing XOR and XNOR logic operations with polarity, each employing a single current conveyor. The proposed polar logic circuits require four MOS switches and two resistors, besides a single CCII+ (second generation current conveyor), in each case. The new proposed circuits are simulated using 0.18 µm CMOS process parameters with a ± 1.8 V supply voltage and reference DC voltage of 1 V, thus enabling polar logic outputs. The polar output for logic 0 and 1 is in form of − 1 V and + 1 V respectively. The results included in support of the work are promising for future applications of the proposal in design of communication circuits. To facilitate better integration prospects, the proposed circuits are further simplified by removing one of the two used resistors and replacing CCII by CCCII (current controlled current conveyor). The simplified polar XOR gate is also verified through simulations. System design applications are expected to evolve from proposed work. The new proposed circuits are expected to significantly contribute to the advancement of circuit design. [ABSTRACT FROM AUTHOR]

In this research work, we propose a new four-dimensional chaotic hyperjerk system with four quadratic nonlinearities. We carry out a detailed bifurcation analysis and derive conditions for the existence of a Hopf bifurcation for the new hyperjerk system. A linear analysis shows that there is only a unique trivial equilibrium state, whose stability depends solely on the parameter p. The only bifurcation possible is a Hopf bifurcation when p = 2. This is verified from bifurcation transition diagrams. We derive new results showing multistability and the existence of coexisting attractors for the new chaotic hyperjerk system. Using MultiSim, a new electronic circuit is designed for the new chaotic hyperjerk system with four quadratic nonlinearities. Finally, we present a control application for the proposed chaotic hyperjerk system with four quadratic nonlinearities. Using active backstepping control, we design a new controller that achieves complete synchronization for the master-slave chaotic hyperjerk systems with four quadratic nonlinearities. [ABSTRACT FROM AUTHOR]

Designing distributed filter circuits (DFCs) is complex and time-consuming, involving setting and optimizing multiple hyperparameters. Traditional optimization methods, such as using the commercial finite element solver High-Frequency Structure Simulator to enumerate all parameter combinations with fixed steps and then simulate each combination, are not only time-consuming and labor-intensive but also rely heavily on the expertise and experience of electronics engineers, making it difficult to adapt to rapidly changing design requirements. Additionally, these commercial tools struggle with precise adjustments when parameters are sensitive to numerical changes, resulting in limited optimization effectiveness. This study proposes a novel end-to-end automated method for DFC design. The proposed method harnesses reinforcement learning (RL) algorithms, eliminating the dependence on the design experience of engineers. Thus, it significantly reduces the subjectivity and constraints associated with circuit design. The experimental findings demonstrate clear improvements in design efficiency and quality when comparing the proposed method with traditional engineer-driven methods. Furthermore, the proposed method achieves superior performance when designing complex or rapidly evolving DFCs, highlighting the substantial potential of RL in circuit design automation. In particular, compared with the existing DFC automation design method CircuitGNN, our method achieves an average performance improvement of 8.72%. Additionally, the execution efficiency of our method is 2000 times higher than CircuitGNN on the CPU and 241 times higher on the GPU. [ABSTRACT FROM AUTHOR]

Noise control is one of the most critical technical indicators to improve the performance of intelligent audio recognition system. Based on the noise cancellation technology, a distributed low noise amplification circuit design was proposed, and the PE15-0P technology was applied to realize broadband low noise amplification. The amplifier circuit used diodes and resistors for voltage division, which effectively achieved bias saturation at the transistor and then diode structure. According to the design of low noise amplifier, the noise output characteristics were simulated and analyzed. An audio enhancement method based on noise type recognition was proposed, which can optimize noise estimation by selecting parameter combinations according to noise type, so as to improve the quality and intelligibility of noise frequency signals in various noise environments. From the aspects of hardware and algorithm design, the noise signal was comprehensively reduced, and the accuracy of audio recognition was significantly improved. [ABSTRACT FROM AUTHOR]

To address the challenges of efficient hardware design for error-tolerant applications, several techniques of applied approximate computing have been proposed. Pruning algorithms aim to approximate circuits with reduced design requirements at the cost of an acceptable degradation of their quality of result. In this letter, we present the effects of resynthesis, an iterative application of logic synthesis along with pruning algorithms, into a state-of-the-art approximate design flow, AxLS. Resynthesis strategy improves the approximation, achieving up to 70% area-power savings for the same error in the output, and reducing the number of iterations, and hence the time required to explore the design space in up to $30\times $ , to obtain an approximated design. [ABSTRACT FROM AUTHOR]

In this research work, we propose a new four-dimensional chaotic hyperjerk system with four quadratic nonlinearities. We carry out a detailed bifurcation analysis and derive conditions for the existence of a Hopf bifurcation for the new hyperjerk system. A linear analysis shows that there is only a unique trivial equilibrium state, whose stability depends solely on the parameter p. The only bifurcation possible is a Hopf bifurcation when p = 2. This is verified from bifurcation transition diagrams.We derive new results showing multistability and the existence of coexisting attractors for the new chaotic hyperjerk system. Using MultiSim, a new electronic circuit is designed for the new chaotic hyperjerk system with four quadratic nonlinearities. Finally, we present a control application for the proposed chaotic hyperjerk system with four quadratic nonlinearities. Using active backstepping control, we design a new controller that achieves complete synchronization for the master-slave chaotic hyperjerk systems with four quadratic nonlinearities.

Abstract This study addresses the intricate challenge of circuit layout optimization central to integrated circuit (IC) design, where the primary goals involve attaining an optimal balance among power consumption, performance metrics, and chip area (collectively known as PPA optimization). The complexity of this task, evolving into a multidimensional problem under multiple constraints, necessitates the exploration of advanced methodologies. In response to these challenges, our research introduces deep learning technology as an innovative strategy to revolutionize circuit layout optimization. Specifically, we employ Convolutional Neural Networks (CNNs) in developing an optimized layout strategy, a performance prediction model, and a system for fault detection and real-time monitoring. These methodologies leverage the capacity of deep learning models to learn from high-dimensional data representations and handle multiple constraints effectively. Extensive case studies and rigorous experimental validations demonstrate the efficacy of our proposed deep learning-driven approaches. The results highlight significant enhancements in optimization efficiency, with an average power consumption reduction of 120% and latency decrease by 1.5%. Furthermore, the predictive capabilities are markedly improved, evidenced by a reduction in the average absolute error for power predictions to 3%. Comparative analyses conclusively illustrate the superiority of deep learning methodologies over conventional techniques across several dimensions. Our findings underscore the potential of deep learning in achieving higher accuracy in predictions, demonstrating stronger generalization abilities, facilitating superior design quality, and ultimately enhancing user satisfaction. These advancements not only validate the applicability of deep learning in IC design optimization but also pave the way for future advancements in addressing the multidimensional challenges inherent to circuit layout optimization.

In this research work, we investigate a new three-dimensional jerk system with three parameters in which one of the nonlinear terms is a sinusoidal nonlinearity. We show that the new jerk system has two unstable equilibrium points on the ��-axis. Numerical integrations show the existence of periodic and chaotic states, as well as unbounded solutions. Consideration of the Poincaré sphere at infinity found no periodic states. We show that the new jerk system exhibits multistability with coexisting attractors. We also present results for the offset boosting of the proposed chaotic jerk system. Using MultiSim version 14.1, we design an electronic circuit for the new jerk system with a sinusoidal nonlinearity. As a control application, we design complete synchronization for the master-slave jerk systems using backstepping control technique. Simulations are presented to illustrate the main results of this research work.

This study addresses the intricate challenge of circuit layout optimization central to integrated circuit (IC) design, where the primary goals involve attaining an optimal balance among power consumption, performance metrics, and chip area (collectively known as PPA optimization). The complexity of this task, evolving into a multidimensional problem under multiple constraints, necessitates the exploration of advanced methodologies. In response to these challenges, our research introduces deep learning technology as an innovative strategy to revolutionize circuit layout optimization. Specifically, we employ Convolutional Neural Networks (CNNs) in developing an optimized layout strategy, a performance prediction model, and a system for fault detection and real-time monitoring. These methodologies leverage the capacity of deep learning models to learn from high-dimensional data representations and handle multiple constraints effectively. Extensive case studies and rigorous experimental validations demonstrate the efficacy of our proposed deep learning-driven approaches. The results highlight significant enhancements in optimization efficiency, with an average power consumption reduction of 120% and latency decrease by 1.5%. Furthermore, the predictive capabilities are markedly improved, evidenced by a reduction in the average absolute error for power predictions to 3%. Comparative analyses conclusively illustrate the superiority of deep learning methodologies over conventional techniques across several dimensions. Our findings underscore the potential of deep learning in achieving higher accuracy in predictions, demonstrating stronger generalization abilities, facilitating superior design quality, and ultimately enhancing user satisfaction. These advancements not only validate the applicability of deep learning in IC design optimization but also pave the way for future advancements in addressing the multidimensional challenges inherent to circuit layout optimization. [ABSTRACT FROM AUTHOR]

This paper proposes a new four-dimensional chaotic system that consists of two active magnetically controlled memristors. The dynamic characteristics of the system, including equilibrium points, Lyapunov exponent spectrum, bifurcation diagram, double-parameter Lyapunov exponent, and attractor basin, are analyzed. The results indicate that the Lyapunov exponents of the system undergo abrupt changes. The bifurcation diagrams reveal the occurrence of sudden cusp bifurcations, and the diverse manifestations of two-parameter Lyapunov exponents under different parameter combinations further underscore the system's complexity and variability. This chaotic system also possesses an infinite number of equilibrium points and coexisting attractors, demonstrating multiple stable states. By adjusting parameters, multi-vortex chaotic attractors with high controllability can be generated, enabling the transition from two-vortex to four-vortex and then to multi-vortex chaotic systems. As the number of vortices increases, the system's dynamic characteristics become richer and more complex. Introducing pulse functions has realized mirrored multi-vortex scroll chaotic attractors, further enhancing the chaotic characteristics of the system. To verify the feasibility and practical value of the mathematical model, a circuit model of the system was constructed. Simulations were conducted using Multisim software, and the system was implemented as a digital circuit using FPGA to validate its feasibility. [ABSTRACT FROM AUTHOR]

Angular velocity is a very important measurement parameter for autonomous driving and industrial applications. The design of MEMS quartz gyro measurement and control circuit has always been the key to restricting the measurement angular velocity performance of gyro system. This paper introduces the application-specific integrated circuit (ASIC) design and implementation of a MEMS quartz gyro measurement and control circuit for angular velocity measurement. The designed nonlinear multiplier can use a square wave to drive the gyro's sensitive structure at the beginning of gyro start-up, thereby reducing the gyro power-up time. The drive circuit replaces the PLL with an automatic gain control unit composed of peak detection and proportional integration (PI) controller, which makes the MEMS gyro system have good robustness. First, SIMULINK is used to model and simulate the MEMS gyroscope system-level model, which illustrates the feasibility of the drive circuit design scheme. Then, the operating principle of the drive loop is analyzed, and the design of the key circuit modules of the measurement and control circuit is introduced. Finally, the performance of the gyroscope drive and detection circuit is experimentally tested, the amplitude and frequency uncertainty of the gyroscope drive circuit are evaluated, and the bias instability and nonlinearity of the gyroscope are tested, the experiment results show that the gyroscope has good performance. [ABSTRACT FROM AUTHOR]

This paper presents a new polar logic circuit using a single current conveyor, two MOS switches and two resistors in each case. Thus, polar NAND and NOR circuits are proposed. The circuits' operation details and simulation results are given in support of the proposed theory. The circuits are designed using CMOS CCII + with ±2 V supply voltage. The polar logic levels at the output are −1 and 1 V for logic 0 and 1, respectively. The gates' functioning for capacitive loading is also tested. The new circuits are expected to be useful in digital and communication systems. [ABSTRACT FROM AUTHOR]

Multi-scroll chaotic systems have complex dynamic behaviors, and the multi-scroll chaotic system design and analysis of their dynamic characteristics is an open research issue. This study explores a new multi-scroll chaotic system derived from an asymptotically stable linear system and designed with a uniformly bounded controller. The main contributions of this paper are given as follows: (1) The controlled system can cause chaotic behavior with an appropriate control position and parameters values, and a new multi-scroll chaotic system is proposed using a bounded sine function controller. Meanwhile, the dynamical characteristics of the controlled system are analyzed through the stability of the equilibrium point, a bifurcation diagram, and Lyapunov exponent spectrum. (2) According to the Poincaré section, the existence of a topological horseshoe is proven using the rigorous computer-aided proof in the controlled system. (3) Numerical results of the multi-scroll chaotic system are shown using Matlab R2020b, and the circuit design is also given to verify the multi-scroll chaotic attractors. [ABSTRACT FROM AUTHOR]

This paper addresses the design of a CMOS modulator to control two quantum bits. The proposed architecture offers several advantages that are addressed and discussed in this paper. The proposed architecture is investigated through both mathematical modeling and Verilog simulations. Moreover, the circuit was designed using the cryogenic Design Kit of the 130 nm SiGe BiCMOS technology of the IHP foundry. The observed agreement between the modeling, Verilog, and transistor-level simulations proves the physical feasibility of the proposed architecture. [ABSTRACT FROM AUTHOR]

The paper presents the results of circuit topological design and layout simulation of the operational amplifier based on complementary (CMOS) structures using the standard industrial planar CMOS technology on KDB-40 silicon wafers with n-type conductivity wells. The operational amplifier was developed for the implementation of an integral converter signals (ICS) of photoplethysmography, the feature of which is the amplitude regulation and filtering of the constant component in the amplified signal from the diode photosensitive element in the wave range of 400 ÷ 1040 nm. The developed ICS is suitable for creating real devices in an integrated implementation, as an element of sensor microsystems-on-a-crystal or smart sensors. [ABSTRACT FROM AUTHOR]

As a noninvasive neuromodulation technique, transcranial magnetic stimulation (TMS) has important applications both in the exploration of mental disorder causes and the treatment of mental disorders. During the stimulation, the TMS system generates the intracranial time-varying induced E-field (E-field), which alters the membrane potential of neurons and subsequently exerts neural regulatory effects. The temporal waveform of the induced E-fields is directly related to the stimulation effect. To meet the needs of scientific research on diversified stimulation waveforms and flexible adjustable stimulation parameters, a novel efficient pulse magnetic stimulation circuit (the EPMS circuit) design based on asymmetric cascaded multilevel technology is proposed in this paper. Based on the transient analysis of the discharge circuit, this circuit makes it possible to convert the physical quantity (the intracranial induced E-field) that needs to be measured after magnetic stimulation into easily analyzable electrical signals (the discharge voltage at both ends of the stimulation coil in the TMS circuit). This EPMS circuit can not only realize monophasic and biphasic cosine-shaped intracranial induced E-fields, which are widely used in the market, but also realize three types of new intracranial induced E-field stimulation waveform with optional amplitude and adjustable pulse width, including monophasic near-rectangular, biphasic near-rectangular and monophasic/biphasic ladder-shaped stimulation waveform, which breaks through the limitation of the stimulation waveform of traditional TMS systems. Among the new waveforms produced by the EPMS circuit, further research was conducted on the dynamic response characteristics of neurons under the stimulation of the biphasic four-level waveform (the BFL waveform) with controllable parameters. The relationship between TMS circuit parameters (discharge voltage level and duration) and corresponding neural response characteristics (neuron membrane potential change and neuronal polarizability ratio) was explained from a microscopic perspective. Accordingly, the biological physical quantities (neuronal membrane potential) that are difficult to measure can be transformed into easily analyzable electrical signals (the discharge voltage level and duration). Results showed that compared with monophasic and biphasic cosine induced E-fields with the same energy loss, the neuron polarization ratio is decreased by 54.5% and 87.5%, respectively, under the stimulation of BFL waveform, which could effectively enhance the neuromodulation effect and improve the stimulation selectivity. [ABSTRACT FROM AUTHOR]

With the rapid development of human society and the surge of engineering construction, the disturbance of the geological environment has grown substantial. The influence of extreme climatic factors and the frequency of geological disasters have increased. Landslide is an important geological disaster. The foundational research in geological disaster detection or monitoring involves studying the physical phenomena associated with the occurrence of landslides, analyzing their signal characteristics, and indirectly determining their development and changes. This scientific area is worthy of in-depth exploration. However, research on the key design and specific implementation of electromagnetic instruments tailored for landslide detection remains lacking. This study is based on the interdisciplinary theoretical system of electronic circuits, embedded computer science, digital signal processing technology, geophysics, and engineering geology. It independently develops a functional prototype of an electromagnetic detector for landslide detection. This design combines the current level of development of electronic disciplines and applies the embedded multicore Da Vinci industrial-grade computer system in the field of earth detection instruments. This study then designs and implements a landslide detection system with independent intellectual property rights. [ABSTRACT FROM AUTHOR]

Photoacoustic imaging (PAI) is gaining attention for its non-invasive diagnostic capabilities. Traditionally, bulky and expensive laser systems have been used as excitation light sources in PAI, posing challenges for translation and remote applications. High-power light emitting diodes (LEDs) can be an alternative light source. However, the necessary driver circuitry has not been extensively studied for driving the nanoseconds pulsed LEDs. This study develops and demonstrate for the first time the full circuit, performance, optimization and operating procedures of a nanosecond pulsed current source (NSPCS) to drive a high-power, high-speed LED array for PAI. The NSPCS driver can deliver tunable pulsed LED currents between 0 and 20 A, pulse widths of 50–100 ns, and trigger pulse repetition rates up to 20 kHz, achieving a driver efficiency of 58.27%. It can drive an array of 37 high-power LEDs (850 nm wavelength) with an electrical-to-optical efficiency of 24.8%. Illumination with this LED array produced a photoacoustic signal (after 79 dB amplification with low-noise amplifier) of 3.92 V (peak-to-peak) and a signal-to-noise ratio of 79.36 dB. The NSPCS circuit has demonstrated effective generation of tunable high-current pulses for LED-based PAI applications.