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This paper describes an application-specific embedded processor with instruction set extensions (ISEs) for the Dynamic Time Warping (DTW) distance measure, which is widely used in time series similarity search. The ISEs in this paper are implemented using a form of logarithmic arithmetic that offers significant performance and power/energy advantages compared to more traditional floating-point operations.

This paper describes an application-specific embedded processor with instruction set extensions (ISEs) for the Dynamic Time Warping (DTW) distance measure, which is widely used in time series similarity search. The ISEs in this paper are implemented using a form of logarithmic arithmetic that offers significant performance and power/energy advantages compared to more traditional floating-point operations.

The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated. In general, available design approaches that adopt dynamic scheduling of instructions add an overhead due to the instruction decoding. To minimize this overhead, several approaches have been introduced, which opt static scheduling. In this context, No-Instruction-Set-Computer (NISC) concept has been introduced to design application-specific processors without an instruction set. NISC concept proposes that there is no need to first design and then use an instruction set when the hardware is programmed by its designers rather than its users. NISC designing approach offers a good compromise between flexibility, productivity, and quality for the design of a digital system. In our work, NISC approach is explored through the design of flexible and efficient architectures dedicated for digital communication applications which fulfill the requirements imposed by multiple emergent communication standards. This paper introduces briefly the NISC concept and the corresponding design methodology. Also, it provides an overview of the related design approach. In addition, the relevance of NISC in realizing flexible and efficient implementation in the domain of digital communication is demonstrated through two case studies on MIMO turbo detection and universal turbo demapping. Both designed NISC-based architectures have been compared to state-of-the-art ASIP-based architectures using similar computational resources and supporting same flexibility parameters. The obtained results show that the proposed NISC-based architectures provide a significant improvement in execution performance while having reduced implementation costs. The results also illustrates how the control memory requirements depend on the application and the devised architecture choices. In the detector module, the adopted re-usability of allocated resources imposes separate controlling of each component; hence, additional control signals are implied. Whereas for the demapper module, implemented hardware components are considered to perform specific operations and to deal with the same type of data; hence, the number of control signals can be reduced significantly. [ABSTRACT FROM AUTHOR]

The proliferation of high-throughput sequencing machines ensures rapid generation of up to billions of short nucleotide fragments in a short period of time. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This paper explores the use of hardware acceleration to significantly improve the runtime of short-read alignment, a crucial step in preprocessing sequenced genomes. We focus on the Levenshtein distance (edit-distance) computation kernel and propose the ASAP accelerator, which utilizes the intrinsic delay of circuits for edit-distance computation elements as a proxy for computation. Our design is implemented on an Xilinx Virtex 7 FPGA in an IBM POWER8 system that uses the CAPI interface for cache coherence across the CPU and FPGA. Our design is $200\times$ faster than an equivalent Smith-Waterman-C implementation of the kernel running on the host processor, $40-60\times$ faster than an equivalent Landau-Vishkin-C++ implementation of the kernel running on the IBM Power8 host processor, and $2\times$ faster for an end-to-end alignment tool for 120–150 base-pair short-read sequences. Further the design represents a $3760\times$ improvement over the CPU in performance/Watt terms. [ABSTRACT FROM AUTHOR]

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multiple-output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm^2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 $\,\times\,$ 4 QR decomposition, 4 $\,\times\,$ 4 singular value decomposition, and 2 $\,\times\,$ 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]–[16]. It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform. [ABSTRACT FROM AUTHOR]

In this study, the authors propose an efficient embedded processing architecture that uses the vascular pattern extraction (VPE) algorithm to authenticate a user to an embedded system. This study first considers the use of direction‐based vascular pattern extraction (DBVPE), and analyses the computational workload involved in running software implementations on an embedded processor. The authors then present a comprehensive performance analysis of the VPE algorithm and examine in detail the various factors that contribute to processing latencies, including VPE recognition processing. In order to improve the efficiency of VPE processing in embedded devices, the authors offer details regarding the process needed to create a highly efficient application‐specific processor and extend the base instruction set of the processor by using custom instructions for recognition processing. The authors implemented our proposed methodology in the context of a commercial extensible processor design flow using the Xtensa platform from Tensilica Inc. Our experiments show that our proposed methodology achieves a 3.95‐fold increase in the vascular pattern recognition speed. Hence, the authors consider our technique to be efficient. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents instruction set architectural guidelines for improving general-purpose embedded processors to optimally accommodate packet-processing applications. Similar to other embedded processors such as media processors, packet-processing engines are deployed in embedded applications, where cost and power are as important as performance. In this domain, the growing demands for higher bandwidth and performance besides the ongoing development of new networking protocols and applications call for flexible power- and performance-optimized engines. The instruction set architectural guidelines are extracted from an exhaustive simulation-based profile-driven quantitative analysis of different packet-processing workloads on 32-bit versions of two well-known general-purpose processors, ARM and MIPS. This extensive study has revealed the main performance challenges and tradeoffs in development of evolution path for survival of such general-purpose processors with optimum accommodation of packet-processing functions for future switching-intensive applications. Architectural guidelines include types of instructions, branch offset size, displacement and immediate addressing modes for memory access along with the effective size of these fields, data types of memory operations, and also new branch instructions. The effectiveness of the proposed guidelines is evaluated with the development of a retargetable compilation and simulation framework. Developing the HDL model of the optimized base processor for networking applications and using a logic synthesis tool, we show that enhanced area, power, delay, and power per watt measures are achieved. [Copyright &y& Elsevier]

We present a novel multiple-input multiple-output (MIMO) decoder accelerator and its associated integrated design environment. The accelerator architecture allows tradeoffs in decoding algorithm, antenna configuration, modulation scheme, and bandwidth at run-time via user programming. The accelerator delivers an improvement over a general purpose digital signal processor (DSP) reaching three orders of magnitude for matrix processing and linear MIMO decoding. The hardware architecture is user-configurable through ten independently set parameters. The parameterization allows independent control over the size and structure of the processing core as well as the structure, size, and access scheme of data memory. We provide a custom high level script and a scalable machine level instruction set and compiler. The elements of hardware configuration and programmability are combined in a user-friendly design flow that takes the MIMO decoder designer from simulation to hardware with dedicated-hardware-like performance in no time. [ABSTRACT FROM AUTHOR]

Clifford algebra (geometric algebra) offers a natural and intuitive way to model geometry in fields as robotics, machine vision and computer graphics. This paper proposes a new representation based on fixed-size elements ( quadruples) of 4D Clifford algebra and demonstrates that this choice leads to an algorithmic simplification which in turn leads to a simpler and more compact hardware implementation of the algebraic operations. In order to prove the advantages of the new, quadruple-based representation over the classical representation based on homogeneous elements, a coprocessing core supporting the new fixed-size Clifford operands, namely Quad-CliffoSor (Quadruple-based Clifford coprocesSor) was designed and prototyped on an FPGA board. Test results show the potential to achieve a 23× speedup for Clifford products and a 33× speedup for Clifford sums and differences compared to the same operations executed by a software library running on a general-purpose processor. [ABSTRACT FROM AUTHOR]

In this paper, we present a multi-input–multi-output (MIMO) decoder accelerator architecture that offers versatility and reprogrammability while maintaining a very high performance-cost metric. The accelerator is meant to address the MIMO decoding bottlenecks associated with the convergence of multiple high-speed wireless standards onto a single device. It is scalable in the number of antennas, bandwidth, modulation format, and most importantly, present and emerging decoder algorithms. It features a Harvard-like architecture with complex vector operands and a deeply pipelined fixed-point complex arithmetic processing unit. When implemented on a Xilinx Virtex-4 LX200FF1513 field-programmable gate array (FPGA), the design occupied 43% of overall FPGA resources. The accelerator shows an advantage of up to three orders of magnitude (1000 times) in power-delay product for typical MIMO decoding operations relative to a general purpose DSP. When compared to dedicated application-specific IC (ASIC) implementations of mmse MIMO decoders, the accelerator showed a degradation of 340%–17%, depending on the actual ASIC being considered. In order to optimize the design for both speed and area, specific challenges had to be overcome. These include: definition of the processing units and their interconnection; proper dynamic scaling of the signal; and memory partitioning and parallelism. [ABSTRACT FROM PUBLISHER]

Group key management is a critical task in secure multicast applications such as Pay-TV over the Internet. The communication group key must be updated and distributed after every change in the group membership. Many solutions have been proposed in the last years to minimize the cost of this rekeying process on the server side. Most of these solutions are tree-based approaches such as the logical key hierarchy. These approaches suffer from three problems. First, tree-based solutions aim at minimizing rekeying costs only by reducing the number of needed cryptographic operations such as encryption or secure hashing. Second, these solutions do not treat the time-consuming digital signing needed to authenticate rekeying messages. Third, tree-based approaches manage huge amounts of keys by software which compromises security. In this paper, a novel hardware/software architecture is proposed, which optimizes the rekeying performance not only by minimizing the number of cryptographic operations, but also by reducing the execution times of these operations including digital signing with the aid of hardware acceleration. All help-keys are generated, managed, and stored on hardware, which enhances the system security. To keep flexibility, control-intensive tasks such as tree management are performed as software functions on the embedded processor. The presented rekeying processor is designed based on a comprehensive security analysis with the aid of a novel illustration for security threats, requirements, and technical solutions, a so-called Security Y-Diagram. A performance measurement on a prototype implementation shows that the rekeying processor can join and disjoin members much faster than software solutions besides supporting much larger groups. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a simulation-based profile-driven quantitative analysis of packet-processing applications. In this domain, demands for increasing the performance and the ongoing development of network protocols both call for flexible and performance-optimized engines. Based on the achieved profiling results, we introduce platform-independent analysis that locates the performance bottlenecks and architectural challenges of a packet-processing engine. Finally based on these results, we extract helpful architectural guidelines for design of a flexible and high-performance embedded processor that is optimized for packet-processing operations in high-performance and cost-sensitive network embedded applications. [Copyright &y& Elsevier]

Abstract: The representation of geometric objects and their transformation are the two key aspects in computer graphics applications. Traditionally, computer-intensive matrix calculations are involved in modeling and rendering three-dimensional (3D) scenery. Geometric algebra (aka Clifford algebra) is attracting attention as a natural way to model geometric facts and as a powerful analytical tool for symbolic calculations. In this paper, the architecture of Clifford coprocessor (CliffoSor) is introduced. CliffoSor is an embedded parallel coprocessing core that offers direct hardware support to Clifford algebra operators. A prototype implementation on a programmable gate array (FPGA) board is detailed. Initial test results show the potential to achieve a 20× speedup for 3D vector rotations, a 12× speedup for Clifford sums and differences, and more than a 4× speedup for Clifford products, compared to the analogous operations in GAIGEN, a standard geometric algebra library generator for general-purpose processors. An execution analysis of a raytracing application is also presented. [Copyright &y& Elsevier]

This paper presents an efficient VLSI architecture for fast implementation of sub-pixel interpolation of H.264/AVC. Several optimization techniques at different design levels, such as parallel processing, vector register, pipeline architecture, and in-place computation, are utilized to reduce the number of memory access and accelerate the interpolation computations. The proposed application-specific processor can meet the real-time constraint of the sub-pixel interpolation algorithm for the 16:9 video format (4,690 × 2,304) at 30 frames per second (fps) at 100 MHz clock rate. [ABSTRACT FROM AUTHOR]

General-purpose processors are often incapable of achieving the challenging cost, performance, and power demands of high-performance applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a processor for a particular application. The processor is extended with hardware in the form of a set of custom function units and instruction set extensions. To effectively identify opportunities for creating custom hardware, a dataflow graph design space exploration engine heuristically identifies candidate computation subgraphs without artificially constraining their size or shape. The engine combines estimates of performance gain, cost, and inherent limitations of the processor to grow candidate graphs in profitable directions while pruning unprofitable paths. This paper describes the dataflow graph exploration engine and evaluates its effectiveness across a set of embedded applications. [ABSTRACT FROM AUTHOR]

• Implementation of parameterizable horizontal/vertical SIMD vector processor architectures. • Performance-optimized hardware and ISA for image processing tasks. • Complete SIFT implementation with detailed horizontal/vertical vectorization strategies. • Extensive architecture comparison for ASIC implementation (performance, area, energy). Embedded automotive Computer Vision systems for real-time motion tracking and 3D scene reconstruction demand for high image feature extraction performance and have a heavily constrained energy budget unable to be met by general-purpose CPUs and GPUs. Due to the required programming flexibility for software updates and algorithmic extensions, the use of fully dedicated hardware accelerators is not advisable in most cases. In this paper, a vertical and a horizontal SIMD vector processor architecture are implemented and compared for accelerating the Scale-Invariant Feature Transform feature extraction algorithm, exploiting inherent data-level parallelism prevalent in this application and considering different programming code strategies for the different vectorization paradigms. An evaluation for a 45 nm ASIC technology shows an overall performance gain of up to 24.8x, and up to 151.3x higher total performance-area-energy efficiency compared to a reference scalar two-issue VLIW processor. Compared to other implementations on programmable ASIP and mobile GPU platforms, the proposed vertical SIMD vector processor achieves a performance gain of up to 5.1x and up to 31.3x higher performance-energy efficiency. [ABSTRACT FROM AUTHOR]