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A two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively. [ABSTRACT FROM AUTHOR]

Among many other applications, electronic converters can be used with sensors with analogue outputs (DC voltage). This article presents an analogue computation converter with two DC voltages at the inputs (one input changes the frequency of the output signal, another input changes the amplitude of the output signal) that provide a periodic sinusoidal signal (with variable frequency and amplitude) at the output. On the basis of the analogue computation converter is a nonhomogeneous second-order linear ordinary differential equation which is solved analogically. The analogue computation converter consists of analogue multipliers and operational amplifiers, composed of seven function circuits: two analogue multiplication circuits, two analogue addition circuits, one non-inverting amplifier, and two integration circuits (with RC time constants). At the output of an oscillator is a sinusoidal signal which depends on the DC voltages applied on two inputs (0 ÷ 10 V): at one input, a DC voltage is applied to linearly change the sinusoidal frequency output (up to tens of kHz, according to two time constants), and at the other input, a DC voltage is applied to linearly change the amplitude of the oscillator output signal (up to 10 V). It can be used with sensors which have a DC output voltage and must be converted to a sine wave signal with variable frequency and amplitude with the aim of transmitting information over longer distances through wires. This article presents the detailed theory of the functioning, simulations, and experiments of the analogue computation converter. [ABSTRACT FROM AUTHOR]

Abstract A two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

Abstract This letter presents the design of a 13.56 MHz offset‐enhanced full‐wave active rectifier, tailored for wirelessly powered biomedical implants. The design incorporates digitally assisted, delay‐compensated active diodes and symmetrical bulk biasing in the rectifier core to enhance conduction time, thus improving the voltage conversion ratio (VCR) and power conversion efficiency (PCE). A delay improvement is achieved both in no‐load and high‐load conditions through an additional comparison path with an offset voltage that is higher than zero. The proposed rectifier is implemented and fabricated in a 180 nm CMOS technology with an area of 0.024 mm2. The rectifier, tested and measured with inductive links, offers a maximum VCR of 96.4% and a maximum PCE of 89%.

This letter presents the design of a 13.56 MHz offset‐enhanced full‐wave active rectifier, tailored for wirelessly powered biomedical implants. The design incorporates digitally assisted, delay‐compensated active diodes and symmetrical bulk biasing in the rectifier core to enhance conduction time, thus improving the voltage conversion ratio (VCR) and power conversion efficiency (PCE). A delay improvement is achieved both in no‐load and high‐load conditions through an additional comparison path with an offset voltage that is higher than zero. The proposed rectifier is implemented and fabricated in a 180 nm CMOS technology with an area of 0.024 mm2$\text{mm}^{\text{2}}$. The rectifier, tested and measured with inductive links, offers a maximum VCR of 96.4% and a maximum PCE of 89%. [ABSTRACT FROM AUTHOR]

Abstract Low‐frequency noise, generated inherently by the number or mobility fluctuation of carriers, is a crucial concern for the design of analog and digital circuits. Unified modelling based on experimental validation of near‐DC noise in amplifiers is a long‐standing open problem. This article develops a model for low‐frequency noise by deriving new bounds for carrier capturing and releasing. According to the proposed model, a measurement system is suggested that operates in a wide frequency range and even at very low frequencies. The system is noise‐tolerant, since the amplifier is selected based on acceptable noise levels. Among the advantages are the independence from specialized structural noise models for each component and the low cost of the measurement system. The evaluation results show that the proposed method leads to a promising improvement in the low‐frequency noise measuring and is superior to conventional models in the normalized root mean square error indicator. Findings reveal that the proposed measurement method can estimate the flicker noise around the DC frequency, and the proposed model agrees reasonably with the proposed measurement circuit.

Abstract In recent years, successive approximation register (SAR) analogue‐to‐digital converters (ADCs) have been widely applied in Internet of Things (IoT) sensor devices. To reduce the power consumption of ADCs, a bridged‐switch energy‐efficient switching scheme for SAR ADCs with a 2× input range is proposed. Due to the use of top‐plate sampling, overall shift and bridged switch, the energy consumption of the first three comparisons and reset is zero, meanwhile the energy consumption of the fifth comparison is greatly reduced. The proposed switching scheme has an average energy consumption of 13.084CVref2, which reduces the switching energy by 99.04% compared to the conventional switching scheme. The proposed switching scheme can achieve a 2× input range with the same supply voltage, effectively reducing ADC power consumption and making it more suitable for IoT applications.

Abstract This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply.

Incipient faults in analogue circuits used in complex electrical systems are hard to diagnose due to weak fault features. To improve the reliability and maintainability of analogue circuits in complex electrical systems, a novel incipient soft fault diagnosis method for analogue circuits based on a multilayer dictionary learning and coding network is proposed, including feature preprocessing, linear dictionary feature encoding, and classification modules. In the first module, time–frequency analyses are performed using continuous wavelet transforms to demonstrate the spectrum maps of the fault signals, while scale-invariant feature transforms are used to enhance local features and obtain the keypoint descriptors of the time–frequency spectrum. In the second module, fault features are obtained by locally constrained linear coding (LLC) method using complete dictionaries from the keypoint descriptors acquired in the previous module, which are captured by linear combination of several adjacent atoms in the dictionary learning. To address the limitations of single-layer dictionary learning methods in complete extraction of fault features, a multilayer learning method is used to get richer fault information and improve the diagnosis accuracy. Finally, the linear output features are captured through pooling and fully connected layers. In the third module, the linear features acquired in the second module are quickly classified with simple linear classifiers. The experimental results demonstrate that the proposed method outperforms existing fault diagnosis methods. In order to verify the effectiveness of the proposed method in analogue circuit fault diagnosis, the Sallen–Key filter circuit and four-op-amp biquadratic filter circuit, which are widely used in the field, are selected as experimental circuits in this paper. Specifically, when the component fault values are offset by 20% of their nominal value, the proposed method achieves accuracies of 99.20% for the Sallen–Key bandpass filter circuit and 98.48% for the four-op-amp biquadratic filter circuit. [ABSTRACT FROM AUTHOR]

Abstract This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V.

Among many other applications, electronic converters can be used with sensors with analogue outputs (DC voltage). This article presents an analogue computation converter with two DC voltages at the inputs (one input changes the frequency of the output signal, another input changes the amplitude of the output signal) that provide a periodic sinusoidal signal (with variable frequency and amplitude) at the output. On the basis of the analogue computation converter is a nonhomogeneous second-order linear ordinary differential equation which is solved analogically. The analogue computation converter consists of analogue multipliers and operational amplifiers, composed of seven function circuits: two analogue multiplication circuits, two analogue addition circuits, one non-inverting amplifier, and two integration circuits (with RC time constants). At the output of an oscillator is a sinusoidal signal which depends on the DC voltages applied on two inputs (0 ÷ 10 V): at one input, a DC voltage is applied to linearly change the sinusoidal frequency output (up to tens of kHz, according to two time constants), and at the other input, a DC voltage is applied to linearly change the amplitude of the oscillator output signal (up to 10 V). It can be used with sensors which have a DC output voltage and must be converted to a sine wave signal with variable frequency and amplitude with the aim of transmitting information over longer distances through wires. This article presents the detailed theory of the functioning, simulations, and experiments of the analogue computation converter.

This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply. [ABSTRACT FROM AUTHOR]

Low‐frequency noise, generated inherently by the number or mobility fluctuation of carriers, is a crucial concern for the design of analog and digital circuits. Unified modelling based on experimental validation of near‐DC noise in amplifiers is a long‐standing open problem. This article develops a model for low‐frequency noise by deriving new bounds for carrier capturing and releasing. According to the proposed model, a measurement system is suggested that operates in a wide frequency range and even at very low frequencies. The system is noise‐tolerant, since the amplifier is selected based on acceptable noise levels. Among the advantages are the independence from specialized structural noise models for each component and the low cost of the measurement system. The evaluation results show that the proposed method leads to a promising improvement in the low‐frequency noise measuring and is superior to conventional models in the normalized root mean square error indicator. Findings reveal that the proposed measurement method can estimate the flicker noise around the DC frequency, and the proposed model agrees reasonably with the proposed measurement circuit. [ABSTRACT FROM AUTHOR]

This paper accounts synchronisation of unified chaotic systems using a modified nonlinear active control technique, its circuit analogue circuit implementation, and secure communication. The proposed nonlinear active control approach utilises appropriate states of the unified chaotic systems. The modified nonlinear active control leads to the coupled error dynamics and does not require the external forcing parameters or gains, which differs from the active control techniques reported in the literature. The designed control law ensures the asymptotic stability in large, and the necessary condition is derived using Lyapunov stability theory. Further, the performance of the designed nonlinear active controller is compared based on different time integral performance of the errors with active, adaptive, and sliding mode control techniques. Numerical and circuit simulations are performed in MATLAB and NI-Multisim environments, respectively. Circuit simulated results accord to MATLAB simulation results. Further, unified chaotic system, its synchronisation, and application to secure communication are validated with breadboard circuit/hardware implementation. [ABSTRACT FROM AUTHOR]

A novel small‐signal detection method that focuses on detection rather than measurement is proposed. It is particularly useful when a sensor is implanted within a living body. Unlike conventional methods, the proposed method detects signals by converting the input signal into a frequency change of an oscillator and monitoring the change in frequency. Its main advantage is the possibility of greatly reducing the circuit size and power consumption compared to conventional methods. To verify the proposed method, a simple implementation experiment using an actual device is performed. Consequently, pulse signals were successfully detected using the proposed method. It is believed that with appropriate implementation, the circuit can detect many types of signals. It is expected that the proposed method can facilitate the collection of small‐signal data and promote its analysis, thereby contributing to the development of various fields.We propose a novel small‐signal detection method that focuses on detection rather than measurement. Its main advantage is the possibility of greatly reducing the circuit size and power consumption compared to conventional methods. We believe that with appropriate implementation, the circuit can detect many types of signals. We expect that the proposed method can facilitate the collection of small‐signal data and promote its analysis, thereby contributing to the development of various fields. [ABSTRACT FROM AUTHOR]

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V. [ABSTRACT FROM AUTHOR]

Abstract This paper proposes a novel curvature‐correction technique insensitive to process variations, which can be used in not only the bandgap reference (BGR) circuit but also the Zener reference circuit. By using two BJT transistors to form a differential pair structure, the current difference between the differential pair generates a compensation current, which compensates for the non‐linearity in the reference voltage. Unlike the classic curvature‐correction technique which can only be used in the BGR circuit, this novel technique can be used in the Zener reference circuit as well. What is more, the proposed curvature‐correction technique is insensitive to process variations, which greatly increases the reliability of commercial products. Finally, simulation results verify the validity of the proposed technique.

In this paper, both grounded and floating type novel designs of inductance simulator, capacitance multiplier simulator and frequency-dependent negative conductance (FDNC) simulator are proposed. Current follower differential input transconductance amplifier (CFDITA) is utilized as active building block in the realization of the proposed works. All the proposed ideas employ grounded capacitor(s) as only passive element(s) which make these designs suitable to modern integration technology. The proposed designs are electronically tunable as transconductance of CFDITA can be varied with bias current. Additionally, the proposed designs have no matching constraints. PSPICE with 0.18 µm CMOS technology process parameters is used to perform simulations of the proposed designs. Experimental verification of functionality of the proposed grounded inductance simulator is also done using commercially available ICs, AD844 and LM13700. The applications of the proposed floating inductance simulator as band-pass filter and band-reject filter are explored. Additionally, proposed grounded FDNC simulator is also tested in third-order high-pass filter to demonstrate the applicability aspects. [ABSTRACT FROM AUTHOR]

In this work, a three-way wide-band in-phase power combiner for ultra-high frequency band (UHF) applications is presented. The proposed power combiner is a modification of the conventional 3-way Wilkinson power combiner. In the proposed power combiner, the floating isolation-resistors are replaced by coaxial baluns and 50-Ω terminations. This configuration is suitable for high-power applications as flange-mount terminations exhibit superior frequency response and heat conduction compared to floating resistors. The coaxial baluns, connected in the star configuration, help for isolation and input-ports matching. The characteristic impedance of coaxial baluns is 50-Ω and is matched to the terminations. This property serves for a broad bandwidth. Even- and odd-mode methods are employed for the analysis and design of the power combiner. To validate the design method and the theoretical results, a three-way power combiner is fabricated, which consists of microstrip, coaxial-cables and some 50-Ω terminations. The combiner provides 20-dB isolation and summing-port return-loss over an octave bandwidth. The operating frequency is between 470 and 860 MHz, which is used for digital video broadcasting–terrestrial (DVB-T). [ABSTRACT FROM AUTHOR]

Abstract This paper proposes a novel bandgap voltage reference (BGR) with low temperature coefficient, ultra‐low noise and without start‐up circuit. Designed in a TSMC 180‐nm CMOS technology, this bandgap voltage reference operates in the temperature range of −55 to 125°C with 5‐V voltage supply and provides a 1.2‐V output voltage VBG. A 16.8 ppm/°C temperature coefficient (TC) and the output RMS noise from 0.1 to 10 Hz of 1.69 µV is achieved. The circuit‐level simulation results verify the presented structure. By the improved architecture of the IPTAT generation stage, the proposed BGR can be powered on normally without designing additional start‐up circuit to eliminate equilibrium point, which greatly simplifies the circuit complexity.

Abstract This letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve a temperature coefficient (TC) of 2.23 ppm/°C. Unlike traditional BGRs, the unique folding compensation method of this circuit improves the performance at low temperature and can also be applied within a specific temperature range.

Abstract The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high‐order systems. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs.

This paper proposes a novel curvature‐correction technique insensitive to process variations, which can be used in not only the bandgap reference (BGR) circuit but also the Zener reference circuit. By using two BJT transistors to form a differential pair structure, the current difference between the differential pair generates a compensation current, which compensates for the non‐linearity in the reference voltage. Unlike the classic curvature‐correction technique which can only be used in the BGR circuit, this novel technique can be used in the Zener reference circuit as well. What is more, the proposed curvature‐correction technique is insensitive to process variations, which greatly increases the reliability of commercial products. Finally, simulation results verify the validity of the proposed technique. [ABSTRACT FROM AUTHOR]

This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design. [ABSTRACT FROM AUTHOR]

This letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve a temperature coefficient (TC) of 2.23 ppm/°C. Unlike traditional BGRs, the unique folding compensation method of this circuit improves the performance at low temperature and can also be applied within a specific temperature range. [ABSTRACT FROM AUTHOR]

This paper proposes a novel bandgap voltage reference (BGR) with low temperature coefficient, ultra‐low noise and without start‐up circuit. Designed in a TSMC 180‐nm CMOS technology, this bandgap voltage reference operates in the temperature range of −55 to 125°C with 5‐V voltage supply and provides a 1.2‐V output voltage VBG. A 16.8 ppm/°C temperature coefficient (TC) and the output RMS noise from 0.1 to 10 Hz of 1.69 µV is achieved. The circuit‐level simulation results verify the presented structure. By the improved architecture of the IPTAT generation stage, the proposed BGR can be powered on normally without designing additional start‐up circuit to eliminate equilibrium point, which greatly simplifies the circuit complexity. [ABSTRACT FROM AUTHOR]

This paper introduces a new nonlinear voltage-mode controller for a PWM dc-dc buck converter operating in continuous conduction mode. The sliding-mode control technique is used to derive a simplified equivalent control law based on the averaged dc-dc buck converter dynamics. As opposed to the reported design approaches, the proposed control scheme only requires the output voltage in the feedback loop without the need to the capacitor current. Thus, the analogue implementation cost is reduced and the drawback of adding a capacitor current sensor to the power converter is eliminated. The control equation is realized in a simple analogue circuit using few op-amps and resistors, which is suitable for industrial applications. The system modeling and control design procedure along with the derivation of the existence and stability conditions are presented. The control system performance is analyzed using MATLAB and SaberRD simulations. Furthermore, a simple analogue prototype of the simplified nonlinear voltage-mode controlled dc-dc buck converter is developed on a PCB. The simulation and experimental results show that the controller maintains a constant switching frequency, exhibits fast transient response, and provides good tracking performance under large disturbances. [ABSTRACT FROM AUTHOR]

Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification‐based test methods. This work presents a built‐in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary‐based diagnosis method. The system is composed of an integrated digital signature generator and a digital control and acquisition subsystem. The signature generator is based on a converter architecture, in which the analogue range can be adapted to the magnitude of the indirect measure using the well known information of the fault‐free circuit. The digital subsystem controls the proposed architecture and stores the digital codes sent by the integrated digital signature generator. The digital signature generator has been designed and fabricated in an industrial 65 nm complementary metal–oxide–semiconductor technology from STMicroelectronics, whereas the digital control and acquisition subsystem have been prototyped in a field‐programmable gate array. The fabricated system has been used to test a biquad filter affected by parametric variations. Successful experimental results are reported showing the capabilities of the proposed adaptive test system to diagnose circuit performances with discrepancies as low as 1% of the actual real value. [ABSTRACT FROM AUTHOR]

The incessant growth of devices such as mobile phones, digital cameras, and other portable electronic gadgets has led to a higher amount of research being dedicated to the low power digital and analogue circuits. In this study, a low power‐delay‐product (PDP) dynamic complementary metal oxide semiconductor (CMOS) circuit design using small swing domino logic with twist‐connected transistors is proposed. An improvement in PDP can be achieved by using a node‐discharger circuit in the conventional design. The conventional benchmark and modified circuits are implemented in 90 nm CMOS technology with different power supplies, i.e. 1.2, 1, and 0.9 V. Furthermore, a decrease in voltage level for logic '1' and an increase in voltage level for logic '0' is achieved while maintaining the logic threshold accordingly at half of the supply voltage. So, the output voltage swing is reduced and the unnecessary nodes of the pull down network get discharged in pre‐charge phase, eventually leading to an improvement when compared with conventional design in overall PDP by 43.21 and 46.83% for two inverted two‐input and three‐input AND gate dynamic benchmarks, respectively, for a power supply of 1 V. [ABSTRACT FROM AUTHOR]

Learning algorithms and devices are an essential part of neural networks and neuromorphic architectures. Astrocyte, as an important element in the learning of neural networks, is believed to play a key role in long‐term synaptic plasticity and memory. In addition, recent experimental observations indicate that astrocytes are active elements in learning in complex networks. In this study, the authors propose a new analogue astrocyte circuit that consumes fewer numbers of transistors compared to its previous counterparts. The authors then use this astrocyte to design a novel analogue circuit to implement a stop‐learning mechanism in a spike‐based learning algorithm and present its neuromorphic very large scale integration (VLSI) simulations. Experimental results demonstrate that the designed circuit can precisely implement the learning mechanisms shown by previous studies implementing spike‐based learning rules without astrocyte. The proposed circuit proposes the first analogue stop‐learning control algorithm that uses astrocytes. It has been designed and simulated in Taiwan semiconductor manufacturing company (TSMC) 0.35 µm complementary metal‐oxide semiconductor (CMOS) technology. [ABSTRACT FROM AUTHOR]

Optimal integer‐order transfer function approximation of linear time‐invariant fractional‐order systems (FOS) using a straight‐forward approach is proposed here. The error between the rational approximant and the FOS (commensurate/non‐commensurate/oscillatory types etc.) is minimised directly in the frequency domain, subject to design stability constraints, by using the colliding bodies optimisation (CBO) algorithm. Comparisons with other well‐known metaheuristics regarding the computational time and the design effort expended in parameter tuning justify the efficiency of the proposed method. The CBO‐optimised models achieve a superior solution quality regarding both the magnitude and phase responses in comparison to the reported literature. Analogue circuit implementations of the models using the current feedback operational amplifier are also presented. Simulations carried out in OrCAD PSPICE environment validate the practical efficacy of the proposed models. [ABSTRACT FROM AUTHOR]

Operational trans‐conductance amplifiers (OTAs) are an essential building block in analogue and mixed‐signal circuits. In this study, a new two‐stage class‐AB OTA is proposed. The class‐AB operation is obtained without extra power dissipation, and without unity‐gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180‐nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC‐gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state‐of‐the‐art designs. [ABSTRACT FROM AUTHOR]

Analogue circuits are one of the most commonly used components in industrial equipment, but circuit failure may lead to significant causalities and even enormous financial losses. To address this issue, in this work the authors propose a new feature extraction scheme based on cross‐wavelet transform (XWT) and variational Bayesian matrix factorisation (VBMF). Primarily, fault signals acquired from defect circuits are collected and processed by using XWT to obtain the joint time‐frequency representation. VBMF is utilised to fetch the time‐frequency information of the fault signal. A nine‐dimensional feature vector is then constructed. Finally, a support vector machine optimised by a flower pollination algorithm is introduced to locate faults. Results show that the proposed approach can effectively locate the different kinds of defection while achieving a higher accuracy. [ABSTRACT FROM AUTHOR]

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

This Letter reports a new no‐equilibrium chaotic system with hidden attractors and coexisting attractors. Bifurcation diagram shows that the proposed system generates chaos through period‐doubling bifurcation with the variation of system parameters, and the hidden chaotic and periodic attractors are visually given by phase portraits. The coexisting chaotic and periodic attractors from different initial conditions are observed in the system. The analogue circuit realisation and microcontroller‐based experimental implementation of the system are given to verify its physical existence. [ABSTRACT FROM AUTHOR]

This study presents low‐power sample and hold (S/H) circuits using second‐generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low‐power consumption, high‐speed and absent from non‐overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single‐ended S/H, differential S/H and serial‐to‐parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 µm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures. [ABSTRACT FROM AUTHOR]

Oscillation Built-In Self-Test (OBIST) strategy allows to avoid the using complex, expensive generators of input test signals during testing, and uses the oscillation frequency generated at the output of the circuit after reconfiguring into oscillator as a controlled parameter. There configuration subcircuit forms an oscillator from the original circuit in the test mode and requires an additional but insignificant area of the chip, especially against the background of stable increasing the scale of integration for the state-of-the-art integrated technologies. Selection of the efficient type of reconfiguration the original circuit into oscillator and implementation of corresponding test circuitry are the most important tasks, which, as rule, are solved nowadays based on experience of designers without automation and therefore restrict to wide use of the OBIST concept. The paper is mainly focused on the task of design-for-testability (DFT) automation with emphasis on the OBIST strategy for analog integrated circuits (IC). The design procedures according to DFT flow are proposed. Three possible structural solutions for reconfiguration of original circuit into an oscillator are considered. The necessary conditions for stability analysis of reconfigured circuit are presented. The stage of a numerical estimating the transient time before the steady-state operation after reconfiguration of original circuit into an oscillator ensuring definition of the start time point for correct calculating the oscillation frequency is proposed. The set of rules for each structural solution for reconfiguration is prepared as the formal procedures, which can support the automation during the DFT flow. The efficiency of the proposed DFT flow is demonstrated for analog circuits, for which the reconfiguration subcircuits were obtained in an automated way during design-for-testability, as well as the fault simulation has been performed. The experimental results for all cases showed the adequacy of oscillation frequency for revealing both catastrophic and parametric faults. Fault coverage for considered set of faults has consisted up to 100 %. [ABSTRACT FROM AUTHOR]

The paper deals with multiple soft fault diagnosis of analogue circuits. A method for diagnosis of linear circuits is developed, belonging to the class of the fault verification techniques. The method employs a measurement test performed in the frequency domain, leading to the nonlinear least squares problem. To solve this problem the Powell minimization method is applied. The diagnostic method is adapted to real circumstances, taking into account deviations of fault-free parameters and measurement uncertainty. Two examples of electronic circuits encountered in practice demonstrate that the method is efficient for diagnosis of middle-sized circuits. Although the method is dedicated to linear circuits it can be adapted to multiple soft fault diagnosis of nonlinear ones. It is illustrated by an example of a CMOS circuit designed in a sub-micrometre technology. [ABSTRACT FROM AUTHOR]

This work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain,KVCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is −111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW. [ABSTRACT FROM AUTHOR]

Proportional to absolute temperature (PTAT) current sources are one of the most important building blocks in analogue circuit design. An important PTAT current source is the Meijer all-NPN cross-quad circuit, where the PTAT output current does not present a strong dependence on the bias current and requires only four matched transistors to be realised, being adequate to be implemented with discrete circuits. In this paper, we present a technique that improves the performance of the Meijer cross-quad PTAT current source and minimises the deviations from the ideal behaviour by simply adding two transistors and adjusting the cell bias voltage. Simulated results in the -40 C to 85°C temperature range show that the errors were reduced by two orders of magnitude by using the novel technique, and a maximum non-linearity of 0.44 ppm/°C was obtained. A prototype of the circuit was built using the LM3046 transistor array, and a maximum deviation from the PTAT ideal current of only 0.06% was measured in 0–80°C, while in the conventional PTAT circuit an error of 0.81% was measured. [ABSTRACT FROM AUTHOR]

In order to simplify the process of analogue circuit fault diagnosis under the premise of improving the fault diagnosis rate of analogue circuit, and to deeply mine the fault characteristics of the output signal, a fault diagnosis method based on convolutional neural network (CNN) is proposed. The output signals in different fault states are directly input into CNN for fault feature extraction and fault classification. By optimising the CNN model and its parameters, the 100% fault diagnosis rate of Sallen‐Key circuit can be achieved. The experimental results indicate that the CNN‐based analogue circuit fault diagnosis method simplifies the fault diagnosis process and improves the fault diagnosis rate. [ABSTRACT FROM AUTHOR]

The paper deals with continuous-time ARC biquadratic (second-order) filters based on the single classical three-port current conveyors, so called second generation CC II. A unique application of the CC II is discussed, when the terminals Y and Z are connected together. Using this way a negative impedance converter is obtained as a suitable building block in synthesis of several biquads, including notch filters.

In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-BJT) on partial buried oxide (PBOX). The novelty of the proposed LAT-BJT device is the use of PBOX, covering just base and emitter regions only. A two-dimensional (2D) calibrated simulation study of the proposed LAT-BJT device has shown that the proposed LAT-BJT on PBOX’s performance is unique when the PBOX is just covering base and emitter regions. At this length of PBOX, a sharp enhancement in cut-off frequency (fT) (~10 times higher) is achieved in the proposed LAT-BJT on PBOX in comparison to an LAT-BJT on silicon-on-insulator (SOI). The breakdown voltage of the proposed LAT-BJT on PBOX is double than that of the LAT-BJT on SOI device at this PBOX length. A notable enhancement in current gain (β) is observed in the proposed LAT-BJT on PBOX in comparison to the LAT-BJT on bulk device. To check the performance of the proposed LAT-BJT on PBOX at the circuit level, two inverters have been designed and simulated using the mixed-mode simulations of Atlas simulator. It has been observed that the proposed LAT-BJT on PBOX significantly outperforms the conventional LAT-BJT device in switching performance. A notable improvement of 32% in ON delay and 72.9% in OFF delay is obtained in the proposed LAT-BJT on PBOX device in comparison to the conventional LAT-BJT device. [ABSTRACT FROM AUTHOR]

This paper presents four new topologies for emulating floating immittance functions. Each circuit uses two or three current-feedback operational-amplifiers (CFOAs) and three passive elements. The proposed topologies can emulate positive/negative lossless and lossy floating inductances, and positive/negative capacitance, resistance and inductance multipliers in addition to floating frequency-dependent positive and negative resistances. The functionality of the proposed circuits is verified using the Advanced Design System software and the AD844 CFOA. The simulation results are in excellent agreement with the theoretical calculations. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel polyphase filter working at high centre frequency using multi-output current differencing transconductance amplifiers (MOCDTAs). The MOCDTA possesses characteristics of low input impedance, high output impedance, wide work frequency and linearly adjustable transconductance. The proposed filter consists of two MOCDTAs, two grounded capacitors, and no resistors. The features of low input impedance and high output impedance make it suitable for cascade. The bandwidth and centre frequency could be adjusted independently by external bias voltage VC and VCa . The image rejection ratio (IRR) could reach 31.6 dB at the centre frequency of 114 MHz, and its bandwidth could be 11.1 MHz. Besides, the centre frequency could be tuned from 38 MHz to 150 MHz with bandwidth of 20.1 MHz. Simulation results which verify the theory are included. [ABSTRACT FROM AUTHOR]