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In this letter, a dynamic channel reservation (DCR) strategy based on deep Q network (DQN) is proposed for multi-service low earth orbit (LEO) satellite communication system. We develop a novel modeling method to represent DCR problem of multiple services as a reinforcement learning (RL) task. Based on this model, we calculate the influence of current channel allocation results on future environment and take it as one of the factors for channel allocation decision. Moreover, a corresponding neural network is designed as a decision evaluator to provide an end to end mapping of decision to its value, which effectively avoids the influence of artificial preconditions. Simulation results show that the proposed strategy can improve the overall quality of service (QOS) of the system.

This paper uses the reconstruction-computation-quantization (RCQ) paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution (DDE). Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding MinSum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ (LS-RCQ), an extension of RCQ decoding for layered architectures. LS-RCQ uses layer-specific message representations to achieve the best possible FER performance. For LS-RCQ, this paper proposes using layered DDE featuring hierarchical dynamic quantization (HDQ) to design LS-RCQ parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered MinSum RCQ decoder with 3-bit messages achieves more than a $10\%$ reduction in LUTs and routed nets and more than a $6\%$ decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset MinSum decoder., This paper has been accepted by IEEE Transactions on Communication

This paper addresses a new scheme by Vasic and Pedagani to combine low-density parity-check (LDPC) codes with run length limited (RLL) constraints. In this method, the RLL constraints are embedded into the LDPC codewords by deliberately flipping the bits of LDPC codewords that violate the RLL constraints. It is important to keep the number of flipped bits small in order to not overburden the LDPC decoder. In this paper, we introduce a method to control the number of flipped bits by using pseudorandom sequences. We present a new low-complexity iterative decoding and detection scheme to correct both the flipped bits and channel errors in a partial response channel. Analyses and simulation results show that the proposed method has good performance and reasonable complexity for (0,k) RLL constraints.

We propose an improved bit-flipping scheme that combines error-correcting codes such as low-density parity check codes with run length limit (RLL) constraints. In addition to its compatibility with soft decision decoding, the proposed scheme has the advantages of no error propagation and fixed block length. Testing with simulated data and real data show good performance. The loss in performance due to the introduction of RLL constraint is less than 0.1 dB at bit-error rate 10/sup -6/ and block-error rate 10/sup -4/.

Non-binary low-density parity-check codes are robust to various channel impairments. However, based on the existing decoding algorithms, the decoder implementations are expensive because of their excessive computational complexity and memory usage. Based on the combinatorial optimization, we present an approximation method for the check node processing. The simulation results demonstrate that our scheme has small performance loss over the additive white Gaussian noise channel and independent Rayleigh fading channel. Furthermore, the proposed reduced-complexity realization provides significant savings on hardware, so it yields a good performance-complexity tradeoff and can be efficiently implemented., Partially presented in ICNC 2012, International Conference on Computing, Networking and Communications. Accepted by IEEE Transactions on Communications

Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. In this paper, we present a new decoding algorithm for the NB-LDPC decoder that is based on the q-ary min-sum algorithm (QMSA). The new one modifies the check node (CN) computations of the QMSA into two steps. By reorganizing the message entries and providing the most likely symbol, a compressed intermediate message can be easily obtained and stored, from which the check-to-variable messages can be computed with a look-up table. Thus the decoder architecture can have a straightforward design for the CN with reduced complexity and memory requirements. Besides, the simulation results demonstrate that the proposed algorithm has negligible performance loss compared to the QMSA over AWGN channel.

The presence of error floor in low density parity check (LDPC) codes is of great concern for potential applications of LDPC codes to data storage channels, which require the error correcting code (ECC) to maintain the near-capacity error correcting performance at frame error rate as low as 10-12. In order to investigate the error floor of LDPC codes under partial response channels used in data storage systems, we propose a new estimation method combining analytical tools and simulation, based on the concept of trapping sets. The definition of trapping sets is based on the dominant error patterns observed in the decoding process. The goal is to accurately estimate the error rate in the error floor region for certain types of LDPC codes under the partial response channel and further extend the frame error rate down to 10-14 or lower. Towards this goal, we first use field programmable gate array (FPGA) hardware simulation to find the trapping sets that cause the decoding failure in the error floor region. For each trapping set, we extract the parameters which are key to the decoding failure rate caused by this trapping set. Then we use a much simpler in situ hardware simulation with these parameters to obtain the conditional decoding failure rate. By considering all the trapping sets we find, we obtain the overall frame error rate in the error floor region. The estimation results for a length -4623 QC-LDPC code under the EPR4 channel are within 0.3 dB of the direct simulation results. In addition, this method allows us to estimate the frame error rate of a LDPC code down to 10-14 or lower.

We present a new class of quasi-cyclic low density parity check (QC-LDPC) codes, whose quasi-cyclic nature makes them attractive for implementation. Both regular and irregular QC-LDPC codes are designed by modifying the progressive edge growth (PEG) graph with a quasi-cyclic constraint. Simulations show that these QC-LDPC codes offer hardware-friendly parity check matrices and have as good error correction performance as random LDPC codes and other good QC-LDPC codes. In addition, the proposed QC-LDPC codes offer a much more flexible set of parameters compared to the traditional designs.

Variable rate and randomized run length limited (VR/sup 2/ RLL) constraint is used in some magnetic tape recording systems. The variable rate encoding algorithm monitors the incoming data stream for conditions such as run length limit (RLL) constraints. If one of the conditions is violated, a bit is inserted into the data stream. The purpose of the VR/sup 2/ RLL constraint is to ensure that the encoded data contains adequate tracking and amplitude information for reliable data detection and prevent the preamble pattern from occurring during the data field. Although the VR/sup 2/ approach to RLL constraint is effective, it has the disadvantages of variable block length and error propagation. Furthermore, VR/sup 2/ is not suitable for soft decision decoding needed by low-density parity check (LDPC) codes being investigated because of their good performance, low complexity and inherent parallel decoding architecture. LDPC codes usually exhibit excellent error correction performance and the LDPC decoder may be able to recover the codeword even if we deliberately introduce some errors in the codeword in order to satisfy RLL constraints. Based on this observation, the paper proposes a scheme of combining LDPC codes with the VR/sup 2/ RLL constraint based on bit flipping. In addition to providing soft decision decoding to achieve large coding gain, the proposed scheme has the advantages of no error propagation and fixed block length.

We propose a bit-flipping scheme of constructing low-density parity-check (LDPC) codes with DC control. The proposed scheme can achieve large coding gain by iterative soft decision decoding and good dc suppression.

We propose a novel iterative decoding algorithm based on partial combination of the parity check matrix for iterative soft decoding of Reed-Solomon product codes. It uses only the simple syndrome equations whose solutions are confined to parts of the columns of the parity check matrix. Compared to other algorithms, the proposed algorithm has lower complexity while offering better performance, which is demonstrated by simulations.

In this article, we present a new scheme that combines the turbo product codes with a simple single carrier frequency domain based equalization algorithm. By using transmit diversity in frequency selective Rayleigh fading channels, the system can resist intersymbol interference effectively. Simulation results show that the proposed system offers diversity gain of more than 6 dB.

Efficient Encoding of Quasi-Cyclic Low-Density Parity-Check Codes Quasi-cyclic (QC) low-density parity-check (LDPC) codes form an important subclass of LDPC codes. These codes have encoding advantage over other types of LDPC codes. This paper addresses the issue of efficient encoding of QC-LDPC codes. Two methods are presented to find the generator matrices of QC-LDPC codes in systematic-circulant form from their parity-check matrices given in circulant form. Based on the systematic-circulation form of the generator matrix of a QC-LDPC code, various types of encoding circuits using simple shift registers are devised. It is shown that the encoding complexity of a QC-LDPC code is linearly proportional to the number of parity bits of the code for serial encoding, and to the length of the code for high-speed parallel encoding.