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As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias (TSV) to electrically connect the wafers, have greatly promoted the technological advances and market development of MEMS in the past ten years. 3D integration enables heterogeneous integration of MEMS and IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems with high performance, low cost, and compact size. This paper first introduces the fundamental fabrication technologies of 3D integration, and then reviews the recent progresses of MEMS and microsystems using 3D integration and TSV technologies. MEMS-CMOS integration, TSV-based wafer level packaging, 2.5D interposer integration of MEMS are illustrated with academic achievements and commercial products by functional categorization. Finally the conclusions are made and the future trends are discussed. © 2008 Elsevier B.V. All rights reserved.

Exposure to a magnetic field at room temperature was found able to promote the dislocation motion and distortion relaxation in silicon. The Kernel average misorientation maps of the silicon samples obtained by electron backscatter diffraction (EBSD) showed that a magnetic field ∼1 T can cause dislocation movement of hundreds of nanometers. And the EBSD image quality maps indicated that the magnetic field can cause the relaxation of the lattice distortion. The Δgmechanism of the magnetically stimulated changes was discussed.

This paper presents a new microplasma generator that can discharge helium gas to produce microplasma with ultra-low breakdown voltages at atmospheric pressure. The generator consists of 2 planar metal electrode arrays and a micro flow channel above the electrodes. The electrode arrays create high electric fields at the electrode gap by applying an AC voltage, which breakdown the working gas flowing through the micro channel. The new generator with low discharge voltages is inspired by the phenomenon discovered in experiments that the discharge voltage decreases when using flowing working gas. Experiments shows that the generator is able to generate stable atmospheric plasmas with a discharge voltage as low as 197 V and a low power consumption of 45 mW; both are the lowest results in literature reports.

This paper reports the design, fabrication, and test of a novel coaxial through-silicon-via (TSV) using low-κ SiO 2 insulator and fabricated on normal silicon substrate for high-frequency applications. The coaxial TSV consists of an annular Cu conductor deposited on the outer sidewall of a central Si post, an annular Cu shielding layer deposited on the inner sidewall of an annular trench that surrounds the Si post, and an annular low-κ SiO 2 insulator in-between the two Cu layers. The low-κ SiO 2 insulator, with the advantage of low cost and good high-frequency performance, is formed by vacuum-assisted spinfilling and thermal curing of liquid precursors. The Cu shielding layer prevents the propagation of electric fields into the lossy silicon substrate and blocks external interferences, and the low-κ SiO 2 insulator reduces the dielectric loss and the parasitics of the TSVs. The measured S 21 and S 11 of TSVs are, respectively, -0.48 dB and -14.91 dB at 10 GHz, and are -1.48 dB and -11.73 dB at 40 GHz, indicating that the coaxial TSVs achieve excellent propagation properties at high-frequency that are impossible for normal TSVs.

This paper reports the design, fabrication, and test of a 3-D integrated uncooled focal plane array (FPA) using monocrystalline silicon diodes as thermosensitive devices. The diode array is fabricated from the silicon device layer of a silicon-on-insulator wafer, and the readout integrated circuits (ROICs) are fabricated on a bulk wafer using the CMOS technology. The silicon diode array is vertically integrated with the ROIC using the 3-D integration technology. Electroless nickel (Ni) plating is developed for fabricating substantial Ni posts to mechanically support the diode pixels to suspension and electrically connect the diode pixels to the ROIC. It allows the integration of monocrystalline device arrays with CMOS circuits fabricated using separate technologies and wafers in vertically suspended configuration. It also improves the filling factors of the FPA chips, shortens the wires between the diodes and the ROIC, and facilitates the releasing process to suspend the diode array. A $160 \times 120$ small-scale FPA has been developed as a test vehicle for concept verification. The test results and successful thermal imaging demonstrate the feasibility of the 3-D integration technology and verify the application of 3-D integration in the development of integrated FPAs using monocrystalline thermosensitive devices.

Silicon nanowire (SiNW) field-effect transistors (FETs) have been developed as various bio/chemical sensors due to their high sensitivity as a result of the huge surface-to-volume ratios. This paper presents a CMOS compatible sidewall mask technology (SMT) for top-down fabrication of SiNWs and a highly sensitive pH sensor based on SiNW FETs. The essence of SMT is to use stand-alone vertical sidewalls of a conformal thin film, fabricated by anisotropically etching away the planar part of the thin film deposited on a thin mesa, as hard masks for SiNW etching. As the feature size of the sidewalls, depending on the film thickness rather than lithography, can be controlled readily to tens to hundreds of nanometers by tailoring the film thickness, SMT allows high output and low cost fabrication of SiNWs without need of advanced lithography facilities. Complete SMT processes have been developed for fabrication of SiNW FETs, and pH sensors using SiNW FETs have been realized. Measurement results show that the pH sensors have good static characteristics and transient performance, and the sensitivity reaches 54.5 mV/pH for a wide range of pH values from 1 to 12, approaching the theoretical Nernstian limit.

To lower the bonding temperature and save the time of the Cu-Cu bonding applied for 3D integration, Ag nanostructure was deposited on the Cu pads as intermediate by femtosecond pulsed laser deposition (PLD). The interface morphology after bonding including oxidation detection and microstructure evolution during high-temperature storage was investigated. The underlying bonding mechanisms were then analyzed and concluded. The element distribution of Ag nanostructures after PLD deposition is detected using the scanning transmission electron microscope equipped with energy dispersive X-ray spectroscopy mapping, and no oxygen is found inside the nanostructures. The electron energy loss spectroscopy shows that no oxidation happens across the Cu-Ag-Cu bonding interfaces during the bonding process by observing the same chemical state of Ag and Cu as the pure metal atom. The as-bonded Cu-Ag-Cu samples were stored at the temperature of 200 °C for 500 h and the microstructure at the bonding interface was observed. Based on the interface microstructure and crystal structure, the physical mechanisms of Cu-Cu bonding using Ag nanostructure as intermediate was explored and summarized in detail. The mechanical interlock between Ag nanostructures, large plastic deformation, surface melting and bulk diffusion are found to simultaneously contribute to the bonding.

This paper reports reactive ion etching (RIE) of poly (cyclohexene carbonate) (PCC), a thermal decomposable polymer that can be used as a sacrificial material for fabrication of embedded micro cavities and channels. The dependence of etching rate and anisotropy on RF power, chamber pressure, and O 2 flow rate has been investigated. Experimental results show that all these parameters have influences on etching rate and anisotropy, and RF power and chamber pressure are, respectively, the two dominant factors that affect etching rate and anisotropy. Etching rate can be increased at high RF power, optimal chamber pressure and optimal O 2 flow rate. Etching anisotropy can be improved by using high RF power, low chamber pressure, and low O 2 flow rate.

Measurement of the electric fields of high-voltage direct-current (HVDC) transmission lines is essential for safety and reliability of power systems. However, air breakdown and corona discharge at the vicinity of HVDC lines create ion flows that induce a charging effect to measurement equipment, causing significant measurement errors. This paper reports an MEMS-based sensor to measure the HVDC fields coupled with ion flows. It consists of two identical chambers and two MEMS electric field sensors that are placed at different levels in the chambers. The chambers use a shielding metal to prevent ion flows from accumulating on the MEMS sensors inside, and thus the electric fields inside the chambers can be measured by the MEMS sensors. The relation between the electric fields inside and outside the chambers is established, and the HVDC fields coupled with ion flows are obtained by using the relation and the measured fields inside the chambers. The design, fabrication, assembly, and test of the MEMS-based sensor are given in detail. The measurement results show that the sensor is able to measure HVDC electric fields coupled with ion flows.

This paper presents a method for fabrication of flexible silicon sensor chips using temporary bonding, backside thinning, debonding, and flexible packaging. Flexibility of silicon chips requires ultrathin thickness, which imposes a challenge to debonding of thinned silicon chips from carrier wafers because of the fragility of silicon. To address this problem, temporary bonding using polypropylene carbonate (PPC), a heat-depolymerizable polymer material, as bonding adhesive is developed. PPC allows damage-free detachment of ultrathin silicon chips from carrier wafers by heating after backside thinning. The method is demonstrated and applied to the fabrication of silicon stress sensor chips with thickness down to $30~\mu \text{m}$ . The measurement results show that the ultrathin silicon chips have good flexibility and function well. The processes are optimized, and the detailed parameters are reported. The preliminary results demonstrate the feasibility of the method, and show its potential application in the fabrication of flexible ultrathin silicon sensors.

This paper presents design, fabrication, and high-frequency characterization of through-silicon-vias (TSVs) with benzocyclobutene (BCB) as the dielectric liner to exploit its low dielectric constant. Fabrication processes for BCB polymer liner TSVs are developed, and BCB-liner TSVs have been successfully fabricated in both low-resistivity silicon and high-resistivity silicon substrates for comparison. A de-embedding method that enables extraction of S-parameters from cascade TSV chains is developed based on the thru-reflect-line calibration algorithm, and the S-parameters of BCB-liner TSVs have been obtained from the measured transmission properties of cascade TSV chains with frequencies up to 25 GHz. Measurement results show that the BCB liner improves transmission properties of TSVs up to 10 GHz compared with SiO2-liner TSVs, and sub-strate resistivity dominates transmission properties for frequencies higher than 10 GHz.

Single-emitting-layer hybrid white organic light-emitting diodes (SEL-hybrid-WOLEDs) are promising candidates for large-area lightings, however, ideal hybrid WOLEDs with a simple structure and high-efficiency, low roll-off, high color rendering index (CRI) and superior CIE coordinates have been rarely reported. In this paper, high-performance SEL-hybrid-WOLEDs are demonstrated by utilizing a thermally activated delayed fluorescence (TADF) host emitter combined with green and red phosphors. The optimized WOLED exhibits an external quantum efficiency (EQE) of 20.2%, CIE coordinates of (0.360, 0.390) and a CRI of 85. Remarkably, an extremely low efficiency roll-off is also realized, with an EQE of 19.4% remained even at the practical luminance of 1000 cd/m 2 , resulting from the wide recombination zone as well as the well-tuned energy transfer in the emitting layer. Moreover, benefited from the stable recombination zone, superior color stability was also achieved. The intriguing results, we believe, greatly manifest the great potential of such a strategy and may pave the way towards real applications.

This paper presents an L-2L de-embedding method for characterizing the electromagnetic properties of through-silicon-vias (TSVs) in 3-D ICs. To the best of our knowledge, this is the first paper that discusses the use of de-embedding method for multiport TSVs. The L-2L de-embedding structure and the analysis algorithm are first introduced. Then, the techniques for meeting two crucial requirements in accurately applying the method on multiport TSVs are proposed. To meet these two requirements, the de-embedding structure is designed to enhance the symmetry and the shielding TSVs are used to decrease the mutual admittance. The simulation results show that with the appropriate design, the shielding TSVs are able to greatly reduce the mutual admittance with little impact on TSVs and RDLs. Finally, the performance of the designed structures with and without shielding TSVs is examined via both full-wave simulation and the measurements. With the full-wave simulation results of TSVs as reference, it turns out that the de-embedding accuracy is significantly improved with the shielding TSVs. Moreover, the de-embedding results based on the measurements show good agreements with those of the simulation ones.

Due to the advantages of ease of fabrication, low cost, and potential high reliability, through-silicon-vias (TSVs) using low-resistivity silicon posts as conductors and circular polymer liners as insulators have been developed for 3-D integration of microelectromechanical systems and microsensors. However, the large coefficients of thermal expansion (CTEs) of polymers lead to significant thermal stresses, which may cause silicon cracks. This paper reports the fabrication, thermal stress simulation, and thermal tests of a silicon TSV using benzocyclobutene (BCB) as the insulator. Silicon TSVs with high-aspect-ratio BCB liners have been fabricated by developing a vacuum-assisted filling method to achieve void-free BCB insulators. Finite-element method (FEM) is employed to simulate the thermal stresses caused by the mismatch in the CTE between silicon and BCB. High-temperature curing experiments show that crack in silicon substrates and silicon posts occurs on TSVs with specific dimensions. By correlating the results of FEM simulations and crack tests, the critical stress that causes silicon cracks is revealed, and design guidelines are proposed to achieve crack-free silicon TSVs.

Three-dimensional integration of microelectromechanical systems (MEMS) and CMOS is able to achieve hetero-integrated microsystems with high performance, small size, low cost, and multiple functions. This paper reports a 3-D integration method using wafer transfer technology and electroless Ni plating with a noncontact induction (ENPNI) technique. Wafer transfer technology based on adhesive bonding and wafer thinning allows stacked integration of MEMS on top of CMOS. To address the challenge in fabricating through-MEMS-vias (TMVs) with small diameters, ENPNI has been developed to fabricate Ni TMVs as both the mechanical supports for suspended MEMS and the electrical connects between MEMS and CMOS. High-density MEMS arrays and CMOS circuits are integrated to demonstrate the feasibility of the 3-D integration method, and thermal cycling and mechanical vibration are performed to evaluate the reliability. Experimental results show that the 3-D integration processes do not exert distinct influences on MEMS arrays and CMOS circuits, and the integrated systems have good yield, uniformity, and reliability. The capability of ENPNI in the fabrication of small TMVs enables 3-D integration of high-density MEMS arrays and CMOS circuits, such as micromirror arrays, infrared focal planes, acoustic sensor arrays, radiation sensor arrays, and so on. [2016-0056]

Using air gaps instead of conventional SiO2 liners as the isolators of through-silicon-vias (TSVs) has the potential for reducing thermal stresses and improving the thermomechanical reliability. This paper reports the thermal test results of newly developed air-gap TSVs with combined air-SiO2 insulators. Fabrication methods based on polymer sacrificial technology are reported. Thermal shock tests between −65 °C and +150 °C are performed, and the results show that the air-SiO2 liner TSVs are reliable over thermal shock with slight improvement in depletion capacitance and capacitance hysteresis. Chip curvatures caused by thermal expansion at high temperatures are measured, and it is found that the air gaps are able to mitigate plastic deformation of Cu plugs at high temperatures. These results indicate that the combined air-SiO2 insulators improve the electrical performance and the thermal stability of air-gap TSVs by isolating the organic residues originated from the sacrificial polymers, and the air-SiO2 liner TSVs have good structural integrity at high temperatures.

The use of air gaps instead of SiO2 as insulators for through-silicon vias (TSVs) has been demonstrated to reduce the thermal stresses and the TSV capacitance of a 3-D integrated system. However, since the Cu plug in air-gap TSVs lacks support and fixation at the sidewalls, the mechanical strength is a serious concern. This paper for the first time reports the mechanical and humidity reliabilities of air-gap TSVs. Reliability tests including free drop test, vibration test, and accelerated moisture test are performed, and the failure mechanisms are analyzed. The residual stresses in silicon substrates are also measured using micro-Raman Spectroscopy. Experimental results show that the premetal dielectric that acts as the only support for Cu plugs is the weak point causing mechanical reliability issues, and oxidation of Cu plugs at high moisture and high temperature is the main reason for humidity reliability problems. Multilayer bonding of TSV chips to constitute a 3-D system remarkably increases the mechanical and humidity reliabilities of air-gap TSVs because of the support and protection provided by the bonding chips.

Objective: The purposes of this study were to measure the orthodontic forces generated by thermoplastic aligners and investigate the possible influences of different activations for lingual bodily movements on orthodontic forces, and their attenuation. Methods: Thermoplastic material of 1.0-mm in thickness was used to manufacture aligners for 0.2, 0.3, 0.4, 0.5, and 0.6 mm activations for lingual bodily movements of the maxillary central incisor. The orthodontic force in the lingual direction delivered by the thermoplastic aligners was measured using a micro-stress sensor system for the invisible orthodontic technique, and was monitored for 2 weeks. Results: Orthodontic force increased with the amount of activation of the aligner in the initial measurements. The attenuation speed in the 0.6 mm group was faster than that of the other groups (p < 0.05). All aligners demonstrated rapid relaxation in the first 8 hours, which then decreased slowly and plateaued on day 4 or 5. Conclusions: The amount of activation had a substantial influence on the orthodontic force imparted by the aligners. The results suggest that the activation of lingual bodily movement of the maxillary central incisor should not exceed 0.5 mm. The initial 4 or 5 days is important with respect to orthodontic treatment incorporating an aligner.

This paper presents a method of achieving high sensitivity for silicon nanowire (SiNW) field-effect transistor (FET) pH sensor by operating the FETs in both capacitive amplification mode and differential amplification mode. The capacitive amplification is implemented by employing an inversed double-gate configuration that uses the electrode immersed in a solution well etched from the backside of the sensor chip as the top gate and the SiNW metal gate as the back gate. This enables the threshold voltages of the FETs to be amplified through the ratio of the top gate capacitance to the back gate capacitance. The differential amplification is achieved by a readout circuit chip that is vertically integrated with the sensor chip using flip-chip bonding. This allows the back gate to be controlled independently by the circuits, such that the differential amplification that is originally applicable to single-gate FETs can be applied to double-gate FETs. By operating the dual amplifications simultaneously, a sensitivity of 720.7 mV/pH has been achieved in the pH range of 4−10. Small deviations between the SiNW pH sensor and a commercial pH meter in measuring phosphate buffer saline, bovine serum, and tap water demonstrate the capability of the SiNW pH sensor in measuring practical samples.

Ternary Ge-Sb-Se chalcogenide glass (ChG) is emerging as an attractive material for fabricating micro optical devices due to the excellent optical properties. This paper reports the reactive ion etching (RIE) of ternary ChG films using CHF3 plasma for patterning microstructures. The influences of the etching parameters, including the ICP power, the chamber pressure, and the gas flow rate, on the etching rate and the anisotropy are investigated and optimized. Grass-like residues are found in high chamber pressure, and the formation mechanism is discussed. The results show that high RF power, low gas flow rate, and low chamber pressure are beneficial to achieving high etching rates and improving good anisotropy. The optimized etching parameters can be used as a baseline for patterning Ge-Sb-Se optical microstructures using reactive ion etching.

Through-silicon-vias (TSVs) with air-gap insulators have the advantages of low capacitance and low thermal stress. This paper reports the design, fabrication, and characterization of new TSVs with combined air/SiO2 insulators. Sacrificial technologies based on heat decomposition of poly(propylene carbonate) and reactive ion etching of benzocyclobutene have been developed to fabricate uniform and high aspect-ratio air gaps. Air gaps with a thickness of 0.8 $\mu \text{m}$ and an aspect ratio of 62.5:1 have been successfully fabricated. Measurement results show that the SiO2 liner is able to eliminate the impacts of residues of the sacrificial polymers, and the TSVs with air/SiO2 have low capacitances and leakage currents at both room temperature and high temperature, constant minimum capacitance, and good temperature stability.

After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies. [2015-0158]

This paper reports a method of fabrication for small-feature-sized nickel (Ni) microbumps on gold (Au) using a newly developed technique called electroless Ni plating with noncontact induction (ENPNI). This technique, differing from conventional electroless Ni plating with contact induction (ENPCI), which directly connects an active metal with an inactive metal to induce Ni electrochemical reaction, is characterized by separation of the active metal and the target metal. The mechanism of ENPNI is interpreted by employing the electric-double layer theory, and some phenomena are explained by the proposed mechanism. Ni microbumps with a diameter of 3–6 $\mu \text{m}$ and a height of 3–4 $\mu \text{m}$ have been successfully fabricated using ENPNI. The resistance of the Ni microbumps is measured, and yield and uniformity are evaluated. By breaking the restriction of contact, ENPNI has the advantages of no need for pretreatment and contact induction, allowing fabrication of microbumps with small feature sizes for applications in which direct contact of an active induction metal is impossible.

A void-free bonding interface is critical to yield and reliability for high-quality wafer bonding. Although adhesive bonding using polymers as the bonding interface material is inherently able to restrain void-formation, for the wafers with uneven patterns like metal interconnects and alignment marks, void-free bonding is still challenging. This paper reports the void-formation in uncured and partially-cured benzocyclobutene (BCB) adhesive for bonding wafers with patterns. Experimental results show that uncured and partially-cured BCB has different behaviors in void-formation, and four types of voids, namely center voids, flower voids, micro voids, and floccules voids, are founded and their formation mechanisms are investigated. By optimizing bonding parameters for uncured BCB bonding, the center voids and flower voids are avoided and void-free bonding can be obtained. For partially-cured BCB, the micro voids and floccules voids tend to appear for uneven wafer surfaces. A reflow pretreatment at 140?C for 2h before curing process is beneficial to reducing the void areas.

Through-silicon vias (TSVs) with air gaps as the isolators have been developed to reduce the TSV capacitance and to solve the reliability problems associated with thermomechanical stresses. This paper reports the reliability assessment of the air-gap TSVs by measuring the $C$ – $V$ , $I$ – $V$ , and resistance of the TSVs in terms of thermal and electrical stresses with a focus on thermal shock, temperature variations, and voltage ramps. Thermal shock tests are performed to evaluate the insulation capability and the thermomechanical stability of the air gaps. Temperature variations are implemented to investigate the influences of high temperatures on the electrical characteristics of the air-gap TSVs. Voltage ramp tests are carried out, and the time-dependent dielectric breakdown is obtained to evaluate the integrity of the air gaps and the intrinsic barrier capability. The preliminary results show that the air-gap TSVs have good thermal stability, excellent dielectric property, and satisfactory structure and barrier stability.

Silicon nanowire (SNW) field-effect transistors (FETs) have proven an emerging highly sensitive bio/chemical sensor due to their huge surface-to-volume ratios. However, fabrication of SNWs with both high output and low cost is still challenging. This paper presents a new fabrication method using sidewall mask technology. By depositing a conformal thin film on a sacrificial pattern and removing the surface film, the vertical part of the film on the pattern sidewall is left as a mask, of which the feature size is determined by the film thickness that can be readily controlled in nanometer regime. This allows wafer-scale, high output, and low cost fabrication of SNWs without need of advanced lithography facilities. The SNWs are operated in a FET configuration by applying gate voltages via a reference electrode immersed into solutions. Demonstrated as a pH sensor, the SNW FETs achieve sensitivity as high as 54.5 mV/pH for pH values from 1 to 12, approaching the theoretical Nernstian limit.

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between -65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.