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Intelligent radar image recognition based on Deep Neural Networks (DNN) has become an important topic in radar information processing. However, DNN models are susceptible to adversarial attacks. Malicious attackers can cause intelligent image recognition models to make incorrect predictions, considerably reducing their recognition accuracy and robustness. This article reviews recent research progress on intelligent radar image recognition countermeasures. Then it summarizes the adversarial attack methods on one/two-dimensional radar image recognition models and adversarial defense methods. Finally, it discusses five open questions worthy of in-depth research in intelligent radar image recognition countermeasures.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

Target misalignment can cause beam pointing deviations and degradation of sidelobe performance. In order to eliminate the effect of target misalignment, we formulate the jamming sub-space recovery problem as a linearly modified atomic norm-based optimization. Then, we develop a deep-unfolding network based on the alternating direction method of multipliers (ADMM), which effectively improves the applicability and efficiency of the algorithm. By using the back-propagation process of deep-unfolding networks, the proposed method could optimize the hyper-parameters in the original atomic norm. This feature enables the adaptive beamformer to adjust its weight according to the observed data. Specifically, the proposed method could determine the optimal hyper-parameters under different interference noise matrix conditions. Simulation results demonstrate that the proposed network could reduce computational cost and achieve near-optimal performance with low complexity.

Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM’s calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply.

Recently, deep unfolding networks have been widely used in direction of arrival (DOA) estimation because of their improved estimation accuracy and reduced computational cost. However, few have considered the existence of a nested array (NA) with off-grid DOA estimation. In this study, we present a deep sparse Bayesian learning (DSBL) network to solve this problem. We first establish the signal model for off-grid DOA with NA. Then, we transform the array output into a real domain for neural networks. Finally, we construct and train the DSBL network to determine the on-grid spatial spectrum and off-grid value, where the loss function is calculated using reconstruction error and the sparsity of network output, and the layers correspond to the steps of the sparse Bayesian learning algorithm. We demonstrate that the DSBL network can achieve better generalization ability without training labels and large-scale training data. The simulation results validate the effectiveness of the DSBL network when compared with those of existing methods.

Multiple access via sparse graph, such as low density signature (LDS) and sparse code multiple access (SCMA), is a promising technique for future wireless communications. This survey presents an overview of the developments in this burgeoning field, including transmitter structures, extrinsic information transform (EXIT) chart analysis and comparisons with existing multiple access techniques. Such technique enables multiple access under overloaded conditions to achieve a satisfactory performance. Message passing algorithm is utilized for multi-user detection in the receiver, and structures of the sparse graph are illustrated in detail. Outlooks and challenges of this technique are also presented. [ABSTRACT FROM AUTHOR]