311 results on '"Zhao, Qing-Tai"'
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2. Low contact resistance of NiGeSn on n-GeSn
3. Vertical GeSn nanowire MOSFETs for CMOS beyond silicon
4. Improved performance of FDSOI FETs at cryogenic temperatures by optimizing ion implantation into silicide
5. Compact modeling of Schottky barrier field-effect transistors at deep cryogenic temperatures
6. Cryogenic characteristics of UTBB SOI Schottky-Barrier MOSFETs
7. Characterization of fully silicided source/drain SOI UTBB nMOSFETs at cryogenic temperatures
8. Room Temperature Lattice Thermal Conductivity of GeSn Alloys
9. Impact of gate to source/drain alignment on the static and RF performance of junctionless Si nanowire n-MOSFETs
10. Vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around nanowire pMOSFETs with NiGeSn contact
11. Transient negative capacitance and charge trapping in FDSOI MOSFETs with ferroelectric HfYOX
12. High Storage and Energy Efficient Memory for Cryogenic Computing
13. A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate
14. Comparison between WKB and Wavelet Approach for Analytical Calculation of Tunneling Currents in Schottky Barrier Field-Effect Transistors
15. High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain
16. Enhanced Device Performance with Vertical SiC Gate-All-Around Nanowire Power MOSFETs
17. Vertical GeSn/SiGeSn GAA Nanowire n-FETs with High Electron Mobility
18. Isothermal Heteroepitaxy of Ge1–xSnx Structures for Electronic and Photonic Applications
19. Ion-sensitive field-effect transistor with sSi/Si0.5Ge0.5/sSOI quantum-well for high voltage sensitivity
20. Experimental demonstration of improved analog device performance of nanowire-TFETs
21. High performance strained Si0.5Ge0.5 quantum-well p-MOSFETs fabricated using a high-κ/metal-gate last process
22. Homogeneous NiSi1−xGex layer formation on strained SiGe with ultrathin Ni layers
23. Ultrathin homogeneous Ni(Al) germanosilicide layer formation on strained SiGe with Al/Ni multi-layers
24. Heterosynaptic Plasticity and Neuromorphic Boolean Logic Enabled by Ferroelectric Polarization Modulated Schottky Diodes
25. Ferroelectric Devices for Neuromorphic Computing
26. (Si)GeSn Isothermal Multilayer Growth for Specific Applications Using GeH4 and Ge2H6
27. Improved LDMOS performance with buried multi-finger gates
28. Toward Low‐Power Cryogenic Metal‐Oxide Semiconductor Field‐Effect Transistors.
29. Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing
30. GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
31. Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature
32. CMOS Beyond Silicon: Vertical GeSn Nanowire MOSFETs
33. Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs
34. (Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs
35. Ultrathin epitaxial Ni-silicide contacts on (1 0 0) Si and SiGe: Structural and electrical investigations
36. Isothermal Heteroepitaxy of Ge1–xSnx Structures for Electronic and Photonic Applications.
37. Formation of a highly Erbium doped silicon-on-insulator layer by introducing SiOx on or into a silicon surface
38. Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations
39. Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory
40. Comparison of strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs: C–V characteristics, mobility, and ON current
41. NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future
42. Four-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses for Neuromorphic Applications
43. Heterosynaptic Plasticity and Neuromorphic Boolean Logic Enabled by Ferroelectric Polarization Modulated Schottky Diodes.
44. Silicon-Based Cooling Elements
45. 4-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses
46. Impact of the Backgate on the Performance of SOI UTBB nMOSFETs at Cryogenic Temperatures
47. Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications
48. Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications
49. Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance
50. (Invited) Vertical Gate All Around GeSn/Ge Heterostructure Transistors
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