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A novel forward and inverse discrete wavelet transformation VLSI architecture for JPEG2000 is proposed. First of all, the reducing scaling coefficients multiplication algorithm (RSCM) was introduced. Then, starting from transform characteristics, the architecture is presented showing both performance and cost. Our implementation is a new architecture that can perform both FDWT and IDWT using filters recommended by JPEG2000. Our architecture has a flexible configuration and high processing speed. The architecture has been implemented in RTL-level Verilog. The estimated number of gates in our proposed architecture in SIMC 0.18-/spl mu/m technology is 15500 and the estimated frequency of operation is 150 MHz.

In this paper, we propose an efficient accelerating architecture for tier-1 coding in JPEG2000. The coding-passes-parallel method is introduced in our architecture to accelerate the encoding. A novel architecture named the scan-window is employed to make it convenient to encode three coding passes in the parallel mode. Therefore, three coding passes can be encoded using one time of bit-plane scan. The processing time can be reduced by more than 70% compared to the traditional serial coding passes processing architecture. Additionally, a pipelined architecture for an MQ coder is proposed to improve the throughout. The architecture has been implemented in SMIC 0.18 /spl mu/m CMOS technology.

We consider the numerical solution of a system of ordinary differential equations, partial differential equations and algebraic equations arising from simulation of radio frequency circuits in which the transistors are described by partial differential equations. An iterative algorithm is presented together with new techniques to find a good initial guess of the solution. The algorithm is applied to the simulation of a voltage-controlled oscillator and the results are compared with those obtained by MEDICI.

This paper reports a 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18 mm 1.8 V 1P6M logic CMOS technology. This cache is designed for a 32-b RISC microprocessor. Effective latency of 3.4 ns and power consumption of 190 mW at 263 MHz are obtained at a supply voltage of 1.8 V. This performance is achieved by using high speed circuit design techniques such as modified high speed current-mode sense amplifier and split dynamic tag comparators.

A 900MHz CMOS PLL using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented. The charge-pump current is insensitive to the changes of temperature and power supply. The value of the charge-pump current can be changed by switches which are controlled by external signals. Thus the performance of the PLL, such as loop bandwidth, can be changed with the change of the charge-pump current. The loop filter initialization circuit can speed up the PLL when power on. A multi-modulus prescaler is used to fulfill the frequency division in the feedback loop. The circuit is designed in 0.18mm 1.8V 1P6M standard digital CMOS process.

High performance architecture for the lifting-based DWT (discrete wavelet transform) is introduced. It has the flexible configuration and high processing speed. The architecture includes the basic control module (BCM), the address generation unit (AGU), one-dimensional wavelet-processing element (WPE) and memory units (MUs). Because of the employ of the pipelining, the whole system is able to achieve to the higher processing speed. Additionally, power consumption and memory requirements can be reduced due to the use of the embedded data extension. The estimated gates are 6600 and the estimated frequency is 300 MHz in the SMIC 0.18mm technology.