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With the arrival of the Sci-Tech era and information era, the standards-essential patent becomes increasingly important and the educational circle is more and more concerned about the study on the anti-monopoly law of standard essential patent. Since many lawsuits on the standards-essential patent occur in recent years, the educational circle of China begins to think seriously over the new legal issue. From the perspective of the anti-monopoly law, this thesis gives an introduction to the concept of standards-essential patent and takes the specific case of Huawei suing the US IDC as an example to analyze how to make use of the anti-monopoly law in China to regulate the standard essential patent .

The Third Plenary Session of the Eighteenth CPC National Congress put forward again that we should adhere to the new path of urbanization with Chinese characteristics, which has attr acted the attention at home and abroad. In the past, the urbanization of our country mainly demonstrated as "land urbanization", which led to the emergence of the local government land finance, widened the gap between urban and rural development, manifeste d interests contradiction between urban and rural areas. Therefore, it is necessary to guarantee that local governments have sufficient sources of fiscal revenue in order to break dependence on land finance for the purpose of making the construction of the new type urbanization becoming the engine for the economic growth in China. The corresponding specific measures are: first, we should perfect the legislation; second, we should straighten out the fiscal power and the administrative authority between the c entral and local governments harmoniously; the last and most important one is that local governments are authorized to adopt the innovative measure of "municipal securities and local taxation system”.

International audience; Corner-based Timing Analysis (CTA) becomes more and more pessimistic as feature size shrinks. This trend has motivated the development of Statistical Static Timing Analysis (SSTA). In this paper, we propose a new path-based SSTA framework that allows the estimation of path delay distributions and delay correlations by propagating iteratively mean and variance of cell delay. These moments, conditioned on input slope and output load values, are pre-characterized by an improved method: log-logistic distribution based input signals and inverters as output load. In applications, the delay gains of this SSTA framework with respect to CTA are shown to be significant. It is also highlighted that the discrepancy of critical paths orderings obtained by SSTA and CTA depends on two factors: cell-to-cell delay correlation and standard deviation of cell delay.

The increase of within-die variations and the design margin growth are creating a need for statistical design methodologies. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts that occur during production. This method is validated for 90nm and 65nm process. Finally, this statistical timing analysis is applied to evaluate, on basic ring oscillators and combinational paths, the timing margins introduced at the design level by the traditional corner based approach.

International audience; Monte Carlo (MC) method is the standard method to characterize statistical moments of cell delays and slopes. However, this method suffers from very high computational cost. In this paper, we propose a technique to quickly and accurately estimate Standard Deviation (SD) of standard cell delays and slopes. The proposed technique is based on the identification, performed with a reduced set of MC simulations, of delay and output slope SD functions that take input slope, output load and supply voltage as input arguments. These identified functions are then used to estimate SDs of delays and slopes at different operating conditions (input slope, output load, supply voltage). This proposed method provides at least % of CPU gains, with respect to MC, while keeping high accuracy.

National audience; To characterize statistical moments of cell delays and slopes, the standard method is Monte Carlo (MC) method. However, this method suffers from very high computational cost. In this paper, we propose a technique to quickly and accurately estimate Standard Deviation (SD) of standard cell delays and slopes. The proposed technique is based on the identification, performed with a reduced set of MC simulations, of delay and output slope SD functions that take input slope, output load and supply voltage as input arguments. These identified functions are then used to estimate SDs of delays and slopes at different operating conditions (input slope, output load, supply voltage). This proposed method provides at least % of CPU gains, with respect to MC, while keeping high accuracy.

International audience; Estimation of delay correlations is one of the most challenging problems in SSTA. This is because cell delay depends on a number of factors in a complex manner, which makes complex the estimation of correlations as well. In this paper, we introduce a technique to compute cell-to-cell and path-to-path delay correlations, which allows considering the effects of cell-level input/output edge, input slope and output lo ad values. Numerical results are presented to quantify its accuracy.

International audience; Statistical Static Timing Analysis (SSTA) is becoming necessary, but has not been widely adopted due to various weaknesses. In this paper, we address one of the challenging problems in SSTA: computation of correlations between cell delays. With the help of conditional moments, cell-to-cell and path-to-path delay correlations are computed by propagating iteratively means and variances of cell delays. This technique of computation allows considering the effects of cell topology, input slope and output load values. Numerical results are presented to quantify its accuracy.

International audience; Statistical Static Timing Analysis (SSTA) is becoming necessary; but has not been widely adopted. One of those arguments against the use is that results of SSTA are difficult to make use of for circuit design. In this paper, by introducing conditional moments, we propose a path-based statistical timing approach, which permits us to consider gate topology and switching process in-duced correlations. With the help of this gate-to-gate delay correlation, differ-ences between results of SSTA and those of Worst-case Timing Analysis (WTA) are interpreted. Numerical results demonstrate that path delay means and standard deviations estimated by the proposed approach have absolute val-ues of relative errors respectively less than 5% and 10%.

International audience; Statistical static timing analysis (SSTA) is becoming complicated due to introduction of more and more advanced statistical techniques. In this paper, with the help of conditional moments, we propose a simple path-based timing approach, which permits us to consider gate topology and switching process induced correlations. Numerical results are presented to quantify the relative impact of these two factors on estimation accuracy of path delay distribution.

International audience; This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of failure probabilities considering device process variations on several long and short paths extracted from a RTL MAC Multiplier-Accumulator physical synthesis. This study is based on a Statistical Static Timing Analysis method, used on combinatory cells, mixed with Monte Carlo Analysis applied on sequential cells. This allows the manipulation of probability distribution functions and thus, to keep all the variability information. Setup time, hold time, and delay propagation variation figures are extracted thanks to this methodology. Several results on combinatory paths and flip-flop cells are given to underline the variability impacts.

National audience; La réduction des dimensions des circuits intégrés a toujours été faite au bénéfice de meilleures performances. Mais aujourd'hui, cette réduction s'accompagne d'un impact croissant des variations du processus de fabrication. Au niveau temporel, on peut ramener ces effets à une probabilité plus élevée de violations des temps de maintien et d'établissement au niveau des bascules. Actuellement, comme principale réponse face à ce problème, les marges de sécurité sont augmentées. Cet article propose une méthodologie d'étude basée sur le concept d'analyse statistique temporelle (SSTA) et de calculs de probabilité de violation. Les résultats obtenus, provenant de son application sur un opérateur arithmétique en technologie 65 nm, permettent d'avoir des informations beaucoup plus précises que celles données par les outils existants, permettant dès lors de meilleures optimisations et une baisse du pessimisme introduit par l'utilisation de marges de conception.