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229 results on '"Zapata, Emilio L."'

3. Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems

Author

Quislant, Ricardo, Gutierrez, Eladio, Zapata, Emilio L., Plata, Oscar, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Dutot, Pierre-François, editor, and Trystram, Denis, editor

Published
2016
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5. Conflict Detection in Hardware Transactional Memory

Author

Quislant, Ricardo, Gutierrez, Eladio, Zapata, Emilio L., Plata, Oscar, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor

Published
2015
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8. Unified Locality-Sensitive Signatures for Transactional Memory

Author

Quislant, Ricardo, Gutierrez, Eladio D., Plata, Oscar, Zapata, Emilio L., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Jeannot, Emmanuel, editor, Namyst, Raymond, editor, and Roman, Jean, editor

Published
2011
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9. Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification

Author

Quislant, Ricardo, Gutierrez, Eladio, Plata, Oscar, Zapata, Emilio L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Fyfe, Colin, editor, Tino, Peter, editor, Charles, Darryl, editor, Garcia-Osorio, Cesar, editor, and Yin, Hujun, editor

Published
2010
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11. Parallel Quantum Computer Simulation on the CUDA Architecture

Author

Gutierrez, Eladio, Romero, Sergio, Trenas, Maria A., Zapata, Emilio L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bubak, Marian, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2008
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12. Memory Locality Exploitation Strategies for FFT on the CUDA Architecture

Author

Gutierrez, Eladio, Romero, Sergio, Trenas, Maria A., Zapata, Emilio L., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Palma, José M. Laginha M., editor, Amestoy, Patrick R., editor, Daydé, Michel, editor, Mattoso, Marta, editor, and Lopes, João Correia, editor

Published
2008
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13. Fast Insolation Computation in Large Territories

Author

Tabik, Siham, Vías, Jesús M., Zapata, Emilio L., Romero, Luis F., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Rangan, C. Pandu, editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Shi, Yong, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2007
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14. Tracking of Linear Appearance Models Using Second Order Minimization

Author

Gonzalez-Mora, Jose, Guil, Nicolas, Zapata, Emilio L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Blanc-Talon, Jacques, editor, Philips, Wilfried, editor, Popescu, Dan, editor, and Scheunders, Paul, editor

Published
2006
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15. Nesting OpenMP and MPI in the Conjugate Gradient Method for Band Systems

Author

Romero, Luis F., Ortigosa, Eva M., Romero, Sergio, Zapata, Emilio L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kranzlmüller, Dieter, editor, Kacsuk, Péter, editor, and Dongarra, Jack, editor

Published
2004
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17. Parallel Algorithm for Fast Cloth Simulation

Author

Romero, Sergio, Romero, Luis F., Zapata, Emilio L., Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Palma, José M. L. M., editor, Dongarra, Jack, editor, and Hernández, Vicente, editor

Published
2001
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20. Fast Cloth Simulation with Parallel Computers

Author

Romero, Sergio, Romero, Luis F., Zapata, Emilio L., Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Bode, Arndt, editor, Ludwig, Thomas, editor, Karl, Wolfgang, editor, and Wismüller, Roland, editor

Published
2000
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24. Set Associative Cache Behavior Optimization⋆

Author

Doallo, Ramón, Fraguela, Basilio B., Zapata, Emilio L., Amestoy, Patrick, editor, Berger, Philippe, editor, Daydé, Michel, editor, Ruiz, Daniel, editor, Duff, Iain, editor, Frayssé, Valérie, editor, and Giraud, Luc, editor

Published
1999
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29. parallelization strategies for the VMEC Program

Author

Romero, Luis F., Ortigosa, Eva M., Zapata, Emilio L., Jiménez, Juan A., Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Kågström, Bo, editor, Dongarra, Jack, editor, Elmroth, Erik, editor, and Waśniewski, Jerzy, editor

Published
1998
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30. Parallel sparse modified Gram-Schmidt QR decomposition

Author

Doallo, Ramón, Fraguela, Basilio B., Touriño, Juan, Zapata, Emilio L., Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Liddell, Heather, editor, Colbrook, Adrian, editor, Hertzberger, Bob, editor, and Sloot, Peter, editor

Published
1996
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37. Teaching the cache memory system using a reconfigurable approach

Author

Quislant, Ricardo, Herruzo, Ezequiel, Plata, Oscar, Benavides, Jose Ignacio, and Zapata, Emilio L.

Subjects
Cache memory -- Study and teaching, Disk caching -- Study and teaching, Computer-generated environments -- Educational aspects, Computer simulation -- Educational aspects, Computer architecture -- Study and teaching, Cache memory, Business, Education, Electronics, Electronics and electrical industries
Abstract

This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing concepts about memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a description of the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory. Index Terms--Cache memories, computer-aided instruction, education, reconfigurable cache design, simulation software.

Published
2008

38. Low-latency pipelined 2D and 3D CORDIC processors

Author

Antelo, Elisardo, Villalba, Julio, and Zapata, Emilio L.

Subjects
Algorithm, Microprocessor, Microprocessor upgrade, Algorithms -- Analysis, Central processing units -- Design and construction, Central processing units -- Analysis, Microprocessors -- Design and construction, Microprocessors -- Analysis, Computer capacity -- Analysis
Published
2008

41. A framework to capture dynamic data structures in pointer-based codes

Author

Corbera, Francisco, Asenjo, Rafael, and Zapata, Emilio L.

Subjects
Pointers (Computers) -- Analysis, Data structures -- Analysis, Computer architecture -- Analysis, Business, Computers, Electronics, Electronics and electrical industries
Abstract

The framework and the analyzer that was implemented to capture complex data structures generated, traversed, and modified in codes based on pointers is described. Several experiments that were carried out with real codes to validate the capabilities of analyzer are also given.

Published
2004

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