Search

Your search keyword '"Zambreno, Joseph"' showing total 255 results
Start Over Author "Zambreno, Joseph"
255 results on '"Zambreno, Joseph"'

1. Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict

Author

Bertram, Joshua R, Wei, Peng, and Zambreno, Joseph

Subjects
Computer Science - Artificial Intelligence
Abstract

Pre-departure flight plan scheduling for Urban Air Mobility (UAM) and cargo delivery drones will require on-demand scheduling of large numbers of aircraft. We examine the scalability of an algorithm known as FastMDP which was shown to perform well in deconflicting many dozens of aircraft in a dense airspace environment with terrain. We show that the algorithm can adapted to perform first-come-first-served pre-departure flight plan scheduling where conflict free flight plans are generated on demand. We demonstrate a parallelized implementation of the algorithm on a Graphics Processor Unit (GPU) which we term FastMDP-GPU and show the level of performance and scaling that can be achieved. Our results show that on commodity GPU hardware we can perform flight plan scheduling against 2000-3000 known flight plans and with server-class hardware the performance can be higher. We believe the results show promise for implementing a large scale UAM scheduler capable of performing on-demand flight scheduling that would be suitable for both a centralized or distributed flight planning system

Published
2020

2. Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels

Author

Qasaimeh, Murad, Denolf, Kristof, Lo, Jack, Vissers, Kees, Zambreno, Joseph, and Jones, Phillip H.

Subjects
Computer Science - Computer Vision and Pattern Recognition, Electrical Engineering and Systems Science - Image and Video Processing
Abstract

Developing high performance embedded vision applications requires balancing run-time performance with energy constraints. Given the mix of hardware accelerators that exist for embedded computer vision (e.g. multi-core CPUs, GPUs, and FPGAs), and their associated vendor optimized vision libraries, it becomes a challenge for developers to navigate this fragmented solution space. To aid with determining which embedded platform is most suitable for their application, we conduct a comprehensive benchmark of the run-time performance and energy efficiency of a wide range of vision kernels. We discuss rationales for why a given underlying hardware architecture innately performs well or poorly based on the characteristics of a range of vision kernel categories. Specifically, our study is performed for three commonly used HW accelerators for embedded vision applications: ARM57 CPU, Jetson TX2 GPU and ZCU102 FPGA, using their vendor optimized vision libraries: OpenCV, VisionWorks and xfOpenCV. Our results show that the GPU achieves an energy/frame reduction ratio of 1.1-3.2x compared to the others for simple kernels. While for more complicated kernels and complete vision pipelines, the FPGA outperforms the others with energy/frame reduction ratios of 1.2-22.3x. It is also observed that the FPGA performs increasingly better as a vision application's pipeline complexity grows., Comment: 8 pages, Design Automation Conference (DAC), The 15th IEEE International Conference on Embedded Software and Systems, 2019

Published
2019

3. Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2

Author

Kempa, Brian, Zhang, Pei, Jones, Phillip H., Zambreno, Joseph, Rozier, Kristin Yvonne, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Bertrand, Nathalie, editor, and Jansen, Nils, editor

Published
2020
Full Text
View/download PDF

16. Automated software attack recovery using rollback and huddle

Author

Sathre, Jesse and Zambreno, Joseph

Abstract

Abstract: While research into building robust and survivable networks has steadily intensified in recent years, similar efforts at the application level and below have focused primarily on attack discovery, ignoring the larger issue of how to gracefully recover from an intrusion at that level. Our work attempts to bridge this inherent gap between theory and practice through the introduction of a new architectural technique, which we call rollback and huddle. Inspired by concepts made popular in the world of software debug, we propose the inclusion of extra on-chip hardware for the efficient storage and tracing of execution contexts. Upon the detection of some software protection violation, the application is restarted at the last known safe checkpoint (the rollback part). During this deterministic replay, an additional hw/sw module is then loaded that can increase the level of system monitoring, log more detailed information about any future attack source, and potentially institute a live patch of the vulnerable part of the software executable (the huddle part). Our experimental results show that this approach could have a practical impact on modern computing system architectures, by allowing for the inclusion of low-overhead software security features while at the same time incorporating an ability to gracefully recover from attack.

Published
2024
Full Text
View/download PDF

19. Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads

Author

Narayanan, Ramanathan, Özıṣıkyılmaz, Berkin, Memik, Gokhan, Choudhary, Alok, Zambreno, Joseph, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Rangan, C. Pandu, editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Shi, Yong, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2007
Full Text
View/download PDF

20. Performance Study of a Compiler/Hardware Approach to Embedded Systems Security

Author

Mohan, Kripashankar, Narahari, Bhagirath, Simha, Rahul, Ott, Paul, Choudhary, Alok, Zambreno, Joseph, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kantor, Paul, editor, Muresan, Gheorghe, editor, Roberts, Fred, editor, Zeng, Daniel D., editor, Wang, Fei-Yue, editor, Chen, Hsinchun, editor, and Merkle, Ralph C., editor

Published
2005
Full Text
View/download PDF

21. CODESSEAL: Compiler/FPGA Approach to Secure Applications

Author

Gelbart, Olga, Ott, Paul, Narahari, Bhagirath, Simha, Rahul, Choudhary, Alok, Zambreno, Joseph, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kantor, Paul, editor, Muresan, Gheorghe, editor, Roberts, Fred, editor, Zeng, Daniel D., editor, Wang, Fei-Yue, editor, Chen, Hsinchun, editor, and Merkle, Ralph C., editor

Published
2005
Full Text
View/download PDF

22. Flow Monitoring in High-Speed Networks with 2D Hash Tables

Author

Nguyen, David, Zambreno, Joseph, Memik, Gokhan, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
Full Text
View/download PDF

23. Exploring Area/Delay Tradeoffs in an AES FPGA Implementation

Author

Zambreno, Joseph, Nguyen, David, Choudhary, Alok, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
Full Text
View/download PDF

49. Providing secure execution environments with a last line of defense against Trojan circuit attacks

Author

Bloom, Gedare, Narahari, Bhagirath, Simha, Rahul, and Zambreno, Joseph

Subjects
Computer science
Abstract

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.cose.2009.03.002 Byline: Gedare Bloom (a), Bhagirath Narahari (a), Rahul Simha (a), Joseph Zambreno (b) Abstract: Integrated circuits (ICs) are often produced in foundries that lack effective security controls. In these foundries, sophisticated attackers are able to insert malicious Trojan circuits that are easily hidden in the large, complex circuitry that comprises modern ICs. These so-called Trojan circuits are capable of launching attacks directly in hardware, or, more deviously, can facilitate software attacks. Current defense against Trojan circuits consists of statistical detection techniques to find such circuits before product deployment. The fact that statistical detection can result in false negatives raises the obvious questions: can attacks be detected post-deployment, and is secure execution nonetheless possible using chips with undetected Trojan circuits? In this paper we present the Secure Heartbeat And Dual-Encryption (SHADE) architecture, a compiler-hardware solution for detecting and preventing a subset of Trojan circuit attacks in deployed systems. Two layers of hardware encryption are combined with a heartbeat of off-chip accesses to provide a secure execution environment using untrusted hardware. The SHADE system is designed to complement pre-deployment detection techniques and to add a final, last-chance layer of security. Author Affiliation: (a) The George Washington University, Department of Computer Science, Academic Center 7th Floor, 801 22nd Street NW, Washington, DC 20052, United States (b) Iowa State University, Department of Electrical and Computer Engineering, 2215 Coover Hall, Ames, IA 50011, United States Article History: Received 30 January 2009; Revised 12 March 2009; Accepted 13 March 2009

Published
2009

Catalog

Books, media, physical & digital resources
See catalog results