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We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull β values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained by the larger ion radius and molecular volume of La2O3 than Y2O3. On the other hand, they are effective in noise reduction, as an effect of interface state density reduction. The key point in fabricating low Vth and highly reliable MOSFETs is the technology for suppression of this interstitial oxygen defect generation.

It was found that critical dimensions of high-k/metal gates obey the multivariate linear approximation with the precision of 3σ=±0.86nm, whose explanatory variables are amounts of metal compounds remaining on the plasma reactor walls. To measure their amounts, the authors assumed they are proportional to amounts of atoms sputtered out by Ar plasma and falling onto a Si wafers placed on a wafer stage. In this study, effects of metal compounds of W, Ti, Ta, and Hf, which are used to construct full-metal/high-k gates, were measured. It was found that Ti and Ta compounds dominate the fluctuation of critical dimensions and the dependency of their amount on wafer numbers being etched obeys a simple difference equation. From these results, they can estimate and minimize the fluctuations of critical dimensions in mass fabrications.

We have proposed a single metal/dual high-k gate stack for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-k dielectrics, such as MgO- and Al2O3-containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.

We investigated the controversial effective workfunction and electron mobility of TiN/HfSiON devices by intentionally adding MgO or La2O3 into HfSiON and by changing the material on TiN or the TiN thickness. As a result, we found a close relationship between the electron mobility at low effective field and the flatband voltage. This relationship is explained on the basis of the fixed charge in HfSiON and its neutralization. The intrinsic workfunction of TiN/HfSiON without charge is determined to be 4.3 eV from the flatband voltage when the electron mobility at low effective field is the highest.

The conduction mechanism of HfSiON stacked-gate dielectric films after a spike annealing is investigated. FETs fabricated using the Damascene process is used to evaluate the electronic characteristics of a stacked-gate dielectric film. The effect of an additional spike annealing after the TiN gate electrode fabrication on the conductivity is analyzed. The electron current over the entire range of gate voltage is increased, while the hole current remains unchanged. The TAT and Schottky analyses derive a consistent energy level of the intermediate trap centers contributing to the electron conduction. The average lifetime is improved by annealing. However, the spike annealing does not change the slope of the TDDB Weibull plots. The average lifetime is improved by annealing. From NBTI analyses, the threshold voltages displayed linearly shifts with increasing injection charge concentration, both with and without the spike annealing. The slope of the threshold voltage shift is defined as a degradation rate.

We have proposed single metal/dual high-k (SMDH) CMISFETs for aggressively scaled devices. The low threshold voltage (Vth) for n- and pMISFETs are obtained by the dual high-k gate dielectrics. The common gate stack for n- and pMISFETs (single metal) is expected to suppress the variation of gate profile. We have successfully demonstrated low-Vth operation of TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs that were fabricated in a gate first process flow. We also investigated the high-k-induced Vth variation that can be another origin of the Vth variation. As a result, we found that TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs do not suffer from high-k-induced Vth variation, but that TiN/HfLaO nMISFETs fabricated by our current process suffer from it. Therefore, we need to optimize the La incorporation process, such as, post-deposition anneal, in order to suppress local high-k-induced Vth variation for TiN/HfLaO nMISFETs.

Film thicknesses of W, TiN, and TaSiN in a full-metal gate stack with photoresist masks were measured in real time during plasma etching with an in situ thickness monitor. The accuracy of such measurement was approximately ±1 nm. The monitor functions on the basis of the interference of plasma optical emission, reflected from the surface and base of the film. Although W and TiN have large absorption indexes, their thicknesses were more accurately measured when they became thinner. In particular, W thickness was estimated more accurately when it was smaller than approximately 10 nm.

We have investigated the time dependent dielectric breakdown (TDDB) for a high-k/metal gate p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) under inversion stress. We have found that electrons, injected from the cathode, are minority carriers in the gate leakage current and play an important role in determining TDDB lifetime and that the existence of oxygen vacancies in HfSiON, decide the electron current mechanism in HfSiON. Since electrons from the cathode flow as a tunneling current with the effective barrier height determined by the energy level of the oxygen vacancies in the HfSiON, electron current is strongly dependent on the effective work function of the metal gate. That implies that a higher work function should be effective to suppress of electron current, due to the elevated barrier height for electrons. Therefore, the formation of a high work function metal gate is essential, not only for low threshold voltage of pMOSFETs but also to achieve long TDDB lifetimes.

We propose a novel approach to control the effective work function by taking advantage of crystal structures in metal gate electrodes. The crystal structures determine the predominant material elements at the metal/high-k interface. We have found that, in a Ru-Mo alloy system, a randomly-oriented Ru (fcc) structure promotes the segregation of Mo at the interface, enabling us to achieve a wide controllability of flatband voltage by the amount of 0.6-0.8 eV. In addition, the segregation of Mo within a Ru-rich electrode is a key to reducing Fermi level pinning at the metal/HfSiON interfaces.

We have investigated the impacts of the nitrogen content in a TaSiNx metal gate on the performance of metal/HfSiON n-type field-effect transistors (FETs). To obtain a low threshold voltage and low electrode resistance, low nitrogen concentration in TaSiNx is preferable. However, the use of a TaSi gate ([N] = 0%) causes the degradation of HfSiON dielectric characteristics such as an increase in leakage current under gate negative bias, positive-bias temperature instability lifetime degradation, time-dependent dielectric breakdown lifetime degradation, and reduction of the electron mobility. Then, a low-nitrogen-concentration TaSiN ([N] = 20%) gate shows the highest electron mobility, excellent reliability characteristics, and low threshold voltage.

RuO2 films were investigated as a work-function-determining metal in metal/high-k gate stacks required for scaled complementary metal–oxide–semiconductor (CMOS) devices. After a low-thermal-budget processing below 400 °C, RuO2 on HfSiON exhibits a high effective work function of about 5.5 eV, which is applicable in p-channel field-effect transistors. However, RuO2 is easily reduced to Ru metal in metal/high-k gate stacks by annealing above 400 °C. Consequently, the high effective work function is unintentionally lowered. This is because RuO2 is thermodynamically unstable when in contact with W and polycrystalline silicon, which are both common components of a metal gate electrode structure. The insertion of TiN and TaN between RuO2 and W does not suppress the reduction. It is concluded that RuO2 is difficult to employ as a metal gate in metal/high-k gate stacks.

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (VTH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low VTH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of VTH roll-offs and Ion-Ioff's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

This paper describes a new NBTI/PBTI evaluation method which uses high-temperature pulsed IV. The benefit of this method is that because the bulk charge is detrapped during the interval before each measurement sequence, only the interfacial component can be extracted. PBTI lifetime of HfSiON, when measured by pulsed IV, is found to be on the line of log(t) vs 1/Vg, contrary to NBTI lifetime which is defined by log(t) vs Vg. Moreover, it is found that temperature dependence of PBTI is smaller than that of NBTI. These findings lead to the conclusion that electric field, rather than thermodynamic energy, affects the reaction at/near Si interface under PBTI stress. PBTI lifetime of TaSiN/HfSiON becomes larger than NBTI lifetime of TiN/HfSiON because of the different Vg dependence.

We have investigated the controllability of the effective work function (phim,eff) of TiN as a work-function-determining metal (WFM) for various gate-electrode structures in HfSiON MOSFETs. phim,eff was controllable from 4.7 to 4.44 eV by changing the TiN thickness from 30 to 2 nm in poly-Si/TiN gate electrodes, without any distinct increase in EOT. Therefore, thin-TiN and thick-TiN WFMs are preferred for the reduction in threshold voltage in nMOSFETs and pMOSFETs with poly-Si/TiN gate electrodes, respectively. A similar controllability was not observed with W/TiN gate electrodes but was evident with W/TaSiN/TiN gate electrodes. This means that controllability is a characteristic of metal gate electrodes with a structure including a Si-rich layer (such as poly-Si and TaSiN)/TiN. It is considered that Ti suboxides, which increase phim,eff as a thin insulator with negative fixed charges, or interface dipoles in the TiN/HfSiON interface, are reduced by oxidation of the Si-rich layer, producing the required result of phim,eff decrease when the TiN thickness becomes as thin as 2 nm.

Accurate determination of the intrinsic diffusivities of boron (B), phosphorus (P), and arsenic (As) in silicon (Si) is reported. We show that the differences in the B, P, and As diffusivities reported in the previous works arise from whether SiO2 films existed on the Si sample surfaces. Impurity diffusion near the Si surface without SiO2 is affected by oxidation of Si even in the nominally inert atmosphere, which has unavoidable residual oxygen background due to the open furnace. On the other hand, a surface SiO2 film of ~20 nm thickness prepared before the diffusion annealing is sufficient to block further oxidation of Si, i.e., truly intrinsic diffusivities of impurities have been obtained from samples having surface oxide layers.

The behavior of traps in physical-vapor-depostited-TiN/SiO2/Si, which had been created in annealing process, was investigated by positron annihilation spectroscopy and X-ray photoelectron spectroscopy. The traps were found to be located at both the TiN/SiO2 and SiO2/Si interfaces, and in the SiO2-bulk. The high-temperature annealing decreased the concentration of the traps in bulk SiO2 and at SiO2/Si interface. Backside X-ray photoelectron spectroscopy (XPS) analysis of TiN/SiO2 suggested the formation of titanium oxynitride (TiON) at the TiN/SiO2 interface, and the amount of TiON formation was reduced by high-temperature annealing. The number of traps at the TiN/SiO2 interface increased with high-temperature annealing, in the case of the increased TiN deposition temperature of 300 °C.

Annihilation characteristics of positrons in SiO2/Si structure were studied by using a monoenergetic positron beam in the temperature range between 50 K and room temperature. In the SiO2 film, positrons formed positronium (Ps) and they annihilated from localized states in open spaces. Below 100 K, the Ps formation was found to be suppressed. This fact was attributed to the trapping of positrons by point defects in the SiO2 film at low temperature. The depth distribution of such traps was not homogeneous; its concentration in the central region of the SiO2 film was higher than that in the regions near the surface or the interface. The potential of monoenergetic positrons for the detection of the point defects provides unique information for depth distributions of hole traps in SiO2 films.

The philosophical and practical differences between Japanese and American IC industries concerning VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing are discussed. A new challenging approach to VLSI reliability is now greatly needed in response to the “paradigm shift” now being brought about by simple scaling limitations, increased process complexity, and VLSI application to advanced systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the “building-in-reliability” approach. To pursue this technique, greater importance will be attached to a deeper physical understanding (including frequent use of Computer Aided Design, CAD/ Design Automation, DA) of the significant relationships between the input variables and product reliability, and to total concurrent engineering from research labs to production sites. In addition, distributive quality control management being carried out particularly in Japan, where quality improvement is the common concern for every employeee, may be a key factor in overcoming the more difficult reliability problems in the coming giga-scale ICs. Furthermore, fast new VLSI testing methods and new yield-enhancing redundancy techniques, resulting in cost reduction, will be increasingly needed to achieve high reliability for VLSIs with 109 devices on a single chip.

To deposit PZT (Pb(Zr,Ti)O3) thin films on Pt films sputtered on thermally oxidized silicon wafers, we used Pb(thd)2, Zr(thd)4, and Ti(iOC3H7)4 as metal-organic chemical vapor deposition sources. The good composition control resulting form the use of Zr(thd)4 provided in-depth uniformity near the interface between Pt and deposited PZT. This uniformity was revealed by TEM observations and in-depth composition analysis using EDX with subnanometer probing radius. PZT films 80 nm thick had a leakage current of 2 × 10−7A/cm2 when the applied voltage was 1.5 V, and equivalent to a SiO2 thickness of 0.4 nm. The variation of composition and thickness over a 4″ wafer was about 1%. This surface uniformity achieved by optimizing the source supply and pumping system, results in the electrical uniform PZT thin films required for fabricating large-scale memory devices.

The annihilation characteristics of positrons in SiO2 films grown on Si substrates were studied by using monoenergetic positron beams. Doppler broadening profiles of the annihilation radiation and lifetime spectra of positrons were measured as a function of incident positron energy for SiO2 (166 nm)/Si specimens fabricated by thermal oxidation. From the measurements, it was found that about 90% of positrons implanted into the SiO2 film annihilate from positronium (Ps) states. This fact was due to the trapping of positrons by open‐space defects and a resultant enhanced formation of Ps in such regions. For the SiO2 film grown at 650 °C, the lifetime of ortho‐Ps was found to be shorter than that in the film grown at 1000 °C. This result suggests that the volume of open‐space defects in the SiO2 film decreased with decreasing the growth rate of the SiO2 film.

We have improved both the spatial resolution and precision of three-dimensional (3D) electron microscopy, which is based on conventional scanning transmission electron microscopy (STEM), by using a micro-pillar specimen together with a 3D analysis holder, and by introducing marker-assisted image alignment prior to 3D reconstruction. Our 3D STEM measurement of aggressively scaled metal-oxide-semiconductor (MOS) gate structures not only successfully showed the z-axis positional dependence of gate-edge profiles and edge-roughness profiles such as line edge roughness (LER) and line width roughness (LWR), but also revealed uniformity of each layer of which the gate structure was composed. Such observations are very important in controlling future device characteristics, but are difficult to obtain using other measurement techniques.

The positron annihilation in a metal‐oxide semiconductor was studied by using a pulsed monoenergetic positron beam. Lifetime spectra of positrons were measured as a function of incident positron energy for a polycrystalline Si(100 nm)/SiO2(400 nm)/Si specimen. Applying a gate voltage between the polycrystalline Si film and the Si substrate, positrons implanted into the specimen were accumulated at the SiO2/Si interface. From the measurements, it was found that the annihilation probability of ortho‐positronium (ortho‐Ps) drastically decreased at the SiO2/Si interface. The observed inhibition of the Ps formation was attributed to an interaction between positrons and defects at the SiO2/Si interface.

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25- mu m phase-shift optical lithography, and its basic operations are verified. A 0.72- mu m/sup 2/ double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A and an access time of 48 ns. >

Elastic recoil detection and Rutherford backscattering were adapted to a stoichiometric study of thin Ta2O5 films deposited on Si substrates by means of the reactive sputtering (SP) and chemical‐vapor‐deposition (CVD) method. Before annealing the samples it was observed that (i) the atomic ratio of oxygen to tantalum in the SP films agreed with 5/2 within the experimental accuracy and (ii) the CVD films have less oxygen content than the other samples. The specimens were annealed for 30 min under the following three conditions: (a) in dry oxygen ambient at 800 °C; (b) in ozone atmosphere under ultraviolet irradiation (UV ozone) at 300 °C; and (c) two‐step treatment of (a) after the (b) process. Each oxidizing process has shown a certain positive effect on the thin CVD samples. Among them, the two‐step treatment has proven to be very effective to restore the stoichiometry of 5/2 in the CVD films. Additionally the thickness of contaminant carbon films on the surface of the samples has been reduced by anneali...

We have successfully suppressed threshold voltage variations due to pattern effect problems and random dopant fluctuation (RDF) using an integrated FSP-FLA technology. The serious problem of the pattern effect in FLA can be solved by using a light-absorber carbon film process, together with FSP-FLA. We estimated the temperature range in our test chip was within 10°C, being the same level obtained with spike RTA. In addition, the diffusion-less feature of FLA reduces the RDF of NMOS down to the same level as with PMOS. By applying several optimized processes, including a high-k/metal gate stack, we achieved A VT as 1.3mVµm for NMOS and 1.2mVµm for PMOS.

Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for V t reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The key to suppress the area scaling dependence is pilling Mg or La atoms up near high-k/IFL interface which enable us increase of stable capping effect. Combination of processing for high-k gate dielectrics and device structure with the high-k dielectrics under offset spacers was found to effectively suppress the V t increase at the 100 nm channel width. As a conclusion, the large capping effect for V t reduction over 400 mV is achieved in scaled devices using this technique.

Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. With this method, we could observe the pre-existing and stress induced defect in high-k. This pre-existing defect affect on MOSFET characteristics. We investigated in detail the relationship between the defect (in bulk high-k and interface) and 1/f noise on (110) and (100) substrates. The 1/f noise is strongly related to the degradation in the hole mobility due to the pre-existing defect or process integration damage. On the other hand, the 1/f noise of nMOSFETs is rerated to interface defects rather than electron mobility degradation.

Millisecond annealing (MSA), such as flash lamp annealing (FLA) and laser spike annealing, is used for dopant activation of ultra-shallow junctions (USJ) in scaled complimentary metal-oxide-semiconductor (CMOS) devices. This is because lower sheet resistance (Rs) and less dopant diffusion are achieved with MSA and these are crucial requirements for minimizing the junction depth (Xj) in state-of-the-art CMOS [1–5]. In FLA the sample is irradiated for a few milliseconds with a Xe-lamp after pre-heating to 500°C or more. The assisted heating is done either using a resistive heater or by irradiation with a halogen lamp. With lamp heating, the assisted temperature (T A ) range is from 500 to 1000°C compared with from 300 to 600°C using a resistive heater. In addition, with lamp assisted heating the temperature profile can be controlled to the second order, similar to spike rapid thermal annealing (sRTA). Thus, we can use higher T A with less dopant diffusion, and higher pre-heat temperatures enable higher peak temperatures during Xe-lamp irradiation. We also used a Flexibly-Shaped-Pulse (FSP) system to control the annealing time and temperature [6–10]. By combining FSP technology with lamp assisted heating, we expect to be able to have control over a wide-range of annealing times and temperatures. In addition, this combination may produce a synergistic effect on device performance. In this report, we examine, first, the effects of high assisted temperatures. Then, we demonstrate the excellent potential of combining FSP technology and lamp assisted heating on device performance.

We have succeeded in suppressing random threshold voltage (V th ) fluctuations by controlling capping-layers and high-k materials with metal gate first stacks for 22 nm-node devices. By employing 1–2 mono Y 2 O 3 -layers on HfSiON films, V th fluctuations are the same as with non-capped samples, while maintaining excellent V th controllability (|ΔV th |≫ 180 mV). Furthermore, the devices exhibit high device performance because ultra-thin equivalent-oxide-thickness (EOT: 0.74 nm) can be achieved with high electron carrier mobility, and very high drain current (I on ≫ 1060 µA/µm) at an I off value of 100 nA/µm.

We studied the impact of Yttrium and Lanthanum incorporation into HfO 2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull β values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained by the larger ion radius and molecular volume of La 2 O 3 than Y 2 O 3 . On the other hand, they are effective in noise reduction, as an effect of interface state density reduction. The key point in fabricating low V th and highly reliable MOSFETs is the technology for suppression of this interstitial oxygen defect generation.

We have developed a carbon absorber process to reduce the pattern effect. This process consists of deposition of carbon, flash lamp annealing (FLA) in an oxygen ambient and SPM-APM wet cleaning. The feature of this process is that the carbon absorber equalizes the light absorption from flash lamps macroscopically and microscopically on the annealed wafer. As a result, we can suppress the pattern effect such that the uniformity of Rs in a 40mm × 40mm area is improved from 11.4 % to 2.1 %. Additionally this process can achieve higher activation than that without the carbon absorber process. We also demonstrate that a flexibly-shaped-pulse FLA (FSP-FLA) can suppress the pattern effect to give a uniformity of 3.4 %. By combining the carbon-absorber process with FSP-FLA, we can achieve 1.6 %. This Rs uniformity of the pattern effect is comparable to that of sRTA.

Fluctuations in not only the number but also the individual carrier capture rate of interface traps in small gate-area MOSFETs containing only less than several interface traps have been investigated from an understanding of newly observed transient charge pumping characteristics. These fluctuations can indicate the possible impact on the fluctuations in threshold voltage of future digital MIS devices.

We have presented functional annealing data using the FSP-FLA, together with some examples of the multi-functionality. First, we showed that the FSP-FLA can control thermal budget whilst sustaining high dopant activation, recovering crystalline defects, and controlling thermal diffusion length. Secondly, by combining impulses from conventional FLA and the trapezoidal pulse of the FSP-FLA, we can improve BTI lifetime and μeff, without degrading Rs-Xj characteristics. In addition, we showed the FSP-FLA pulse for preheat control. Therefore, we have a high confidence that FLA has evolved to the 2nd generation with the FSP-FLA system and it will be a main-stream annealing method for scaled high-k/metal gated devices in the near future.

We investigated the influence of extremely high doping concentrations on the sheet resistance of ion implants annealed by FLA. As the implant depth was ultra-shallow and the amount of dopant atoms high, the concentration of dopant near the surface was exceedingly high, above the solid solubility limit, resulting in high Rs. The cause of this is mainly due to the formation of clusters, which was confirmed by calculation and experimental data. The clustering was occurred during the preheating process before the Xe-lamp flash irradiation.

We investigated in detail the relationship between the 1/ƒ noise, carrier mobility and interface state defects between the Si substrate and oxide on (110) and (100) substrates. In the case of pMOSFETs, the 1/ƒ noise is independent of the mobility degradation due to the increase of effective hole mass in Si channel. However, the 1/ƒ noise is strongly related to the degradation in the hole mobility due to the process integration damage. With hole mobilities becoming lower, 1/ƒ noise intensity was enhanced. On the other hand, the 1/ƒ noise of nMOSFETs is rerated to interface defects rather than electron mobility degradation. Additionally its behavior was affected by the difference between P b0 and P b1 .

We have theoretically analyzed the mechanism of PBTI degradation of high-k gate dielectrics. We proposed a PBTI degradation model based on a comprehensive physical theory using the general notation of gate leakage current and adequate trap distribution. Furthermore, by taking account not only pre-existing but also stress-induced defects, our model could explain the experimental data with high accuracy even though it was very simple. In addition, we have clarified that defect generation rate and/or capture cross-section in HfSiON is different from that in HfLaSiON.

Thermal changes of implanted fluorine distributions in a SiO2 film and a (100)‐oriented Si single crystal were investigated by the 19F(p, αγ) 16O reaction and secondary‐ion mass spectrometry. Fluorine in the Si accumulates to a damaged region (consistent with a Monte Carlo simulation) after annealing above 700 °C for 30 min. This effect is not observed in the SiO2. Once the fluorine is trapped by the damaged region, nearly 80% of the fluorine stays in the silicon after annealing at 800 °C. In contrast, only 10% of implanted fluorine remains in the SiO2 after annealing at 800 °C. These effects are explained by assuming the difference in the natures of imperfections in these samples. Above 1000 °C, most of the fluorine diffuses out of both systems.

We present a systematic examination of Vth controllability using Y2O3, La2O3, and MgO2 layers by atomic-layer-deposition (ALD) technology with HfSiON/TaSiN gate first stacks for half-pitch (hp) 32 nm-node metal gated bulk devices. By employing base-Y2O3 layers of 1 mono-layer (ML 130 mV), high electron carrier mobility, and very high drain current (> 1100 muA/mum) at a low Ioff value (100 nA/mum). Moreover, the positive-bias-temperature-instability (PBTI) over a 10-year lifetimes can be readily achieved with Vg= +1.0 V at 125degC.

We have clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB). Although La incorporation is effective for pre-existing defect suppression, stress induced defect generation is more sensitive to stress voltage and temperature. This is caused by the elevation of the energy level of oxygen vacancy and high ionicity of La-O bond. The origin of defects is thought to be oxygen vacancy related defects, generated under positive stress and they are common to PBTI and TDDB degradation.