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Methods of improving Fermi-level pinning of pure metal gate electrodes on Hf-based high-k dielectrics have been investigated. The pinning phenomenon is a crucial problem, resulting in an unintentional threshold voltage increase in p-MOSFETs when applying pure metal gate electrodes such as Ru and TiN in Hf-based high-k CMOS. After systematic investigation of the relation between oxygen vacancies in Hf-based high-k dielectrics and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. It is necessary to modulate the stable pinning energy position of Hf-based high-k dielectrics in p-MOSFETs in order to obtain thin EOTs in the gate-first process.

Leakage current characteristics with significantly reduced dispersion were achieved for HfSiON gate dielectric film by selecting TiN gate electrode with low reactivity, compared to the conventional poly-Si gate. The breakdown lifetime and its characteristic homogeneity were also enormously improved. With intensive study on these electrical characteristics, it was concluded that the concentration of oxygen vacancy was significantly reduced, giving rise to the homogeneity improvement. Moreover, we have shown an explanation for the dielectric breakdown in terms of oxygen transport in the Hf-based dielectric film.

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We have established a comprehensive understanding of the PBTI and NBTI reliability of high-k/metal gate stacks. PBTI is found to exhibit a universal relationship, in terms of fast transient carrier traps and stress voltage, due to the formation of positive oxygen vacancies. The use of metal gates for Tinv scaling is promising for the improvement of drain current without PBTI lifetime degradation. However, in the case of NBTI, interface state degradation becomes more serious with Tinv scaling. Thus, the use of a high quality interfacial layer, such as a wet oxide interface, is a promising solution for the improvement of NBTI lifetime.