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An improved VBIC model for InP/InGaAs double heterojunction bipolar transistors (DHBTs) is proposed. The model accounts for the double heterojunction effect and current blocking effect with novel current expressions. New empirical formulas for the collector-base capacitance and transit time are developed to explain the mobile-charge modulation effect and the role of negative differential mobility. DC and S-parameter measurements are conducted in order to realize the whole extraction flow. The accuracy and validity of this new model and extraction strategy are demonstrated by comparisons of simulation to measurement data on DC, AC small-signal and large-signal characteristics over a wide bias region.

The design and measured results of a broad-band direct quadrature phase shift keying (QPSK) modulator and demodulator are described in this paper. The circuits are fabricated using 1-μm GaAs HBT technology. To suppress the local oscillator (LO) leakage, the double-balanced mixer is selected as the core unit in the modulator/demodulator. An embedded four-way quadrature divider which includes a Lange coupler and two Baluns is utilized in the system to generate quadrature-phase LO signals. As results of a back-to-back test, the system can operate at data rates in excess of 2 Gb/s (1 Gb/s per I and Q channels) at 30 GHz. The supplies of the modulator and demodulator are 5.0 V and 4.5 V with size of 1.35 mm×3.5 mm and 1.36 mm×3.4 mm, respectively.

A W-band two-stage amplifier MMIC has been developed using a InP-based high electron mobility transistor (HEMT) technology. The two-stage amplifier has been realized in combination with coplanar waveguide topology and cascode transistors, thus leading to a compact chip-size of 1.85 mm×0.932 mm and an excellent small-signal gain of 25.7 dB at 106 GHz. The successful design of the two-stage amplifier MMIC indicates the InP HEMT technology has a great potential for W-band applications.

A two-stage double heterojunction bipolar transistor (DHBT) power MMIC fabricated in InP technology is realized using coplanar waveguide structure. The output cell unit consists of four parallel cascode fingers. Sixteen fingers are at output stage from which the power is combined. Broad-band, low-loss matching networks lead to high gain and high combining efficiency. The chip area is 1.5×1.7 mm2. Measurements show that small signal gain is above 20 dB over 75.5 GHz ∼ 84.5 GHz frequency band. Simulated saturated power is 19.7 dBm @ 89 GHz and the actual output power is to be measured once the W-band power source arrive.

Two MMIC amplifiers have been developed in coplanar technology using 50-nm InAlAs/InGaAs HEMTs. The first is a sing-stage amplifier which used balanced double-stub matching networks for both input and output impedances matching. Measured gain is 8.2 dB @ 81.3 GHz, and the 3-dB bandwidth is at least 13.7 GHz. The second is a two-stage common-source power amplifier. A “#” type distributed transmission line networks has been developed and applied to inter-stage and output stage matching networks. This technique propose a new and efficient approach for impedance matching between transistors where DC blocking and separate bias supplies to the active devices are required. Measured gain is 10.1 dB @ 84 GHz and the 3-dB bandwidth is 14.7 GHz. The saturated power is 11.6 dBm @ 85 GHz, 3.6 dB higher than the above-mentioned single-HEMT amplifier. Measured data are in agreement with the simulation results.

A W-band frequency doubler MMIC is designed and fabricated using 1-μm InP DHBT technology. Active balun is employed to transform the single-ended signal into differential output. Push—push configuration loaded with harmonic resonant network is utilized to acquire the second harmonic frequency. A multi-stage differential structure improves the conversion gain and suppresses the fundamental frequency. The MMIC occupies an area of 0.55 × 0.5 mm2 with 18 DHBTs integrated. Measurements show that the output power is above 5.8 dBm with the suppression of fundamental frequency below −16 dBc and the conversion gain above 4.7 dB over 75–80 GHz.

A two-stage MMIC power amplifier has been realized by use of a 1-μm InP double heterojunction bipolar transistor (DHBT). The cascode structure, low-loss matching networks, and low-parasite cell units enhance the power gain. The optimum load impedance is determined from load-pull simulation. A coplanar waveguide transmission line is adopted for its ease of fabrication. The chip size is 1.5 × 1.7 mm2 with the emitter area of 16 × 1 μm × 15 μm in the output stage. Measurements show that small signal gain is more than 20 dB over 75.5–84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB. The high power gain makes it very suitable for medium power amplification.