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openaire: EC/H2020/704947/EU//ADVANTAG5 This article presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board. The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back off efficiency. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by ON/OFF logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation. Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die. Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated Long Term Evolution (LTE) signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz.

openaire: EC/H2020/704947/EU//ADVANTAG5 Modern wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this article, we introduce a blocker-tolerant harmonic rejection (HR) receiver, which can suppress blockers at the local oscillator harmonics. The suppression is achieved by applying the HR in two stages, such that the first HR already occurs at the first gain-stage output. The proposed receiver achieves this HR with a simple six-phase local-oscillator (LO) clocking. The proposed design also uses simple gain coefficients of ±1 while implementing HR in two stages that compensates for the mismatch effects of each stage. In addition, the near-band blocker linearity is improved by implementing a third-order baseband feedback response, which acts in conjunction with the N -path filtering. Implemented in a 28-nm Fully-Depleted Silicon-on-Insulator (FDSOI) process, the receiver demonstrates the 18-37-dB HR from the first stage and 46-53 dB of HR in total. Furthermore, a blocker compression point (BCP) of 2.5 dBm fora third harmonic blocker and a near-band BCP of -6.5 dBm are achieved.

This paper describes the design and measurement of an open-loop fractional frequency divider implementation. The fractional divider consists of a multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator. The fractional frequency division is achieved with the MMD and the 13-bit SDM toggling the integer division ratio. The resulting signal is then processed by the phase interpolator which significantly reduces the spurs by 22 dB and generates spectrally clean signal with correct output frequency. The prototype is implemented in 28-nm CMOS technology and it operates within input frequency range of 1.9 GHz–3.5 GHz with fractional division ratio in between 2–3. As an example of the operation, with a setting of an arbitrary division ratio of 2.3164 and input frequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.

openaire: EC/H2020/704947/EU//ADVANTAG5 This paper proposes a wideband 2-5GHz LO phase-shifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering direct conversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm.sq.

Results of theoretical and experimental investigations of full-metal slot reflectarray antennas with increased bandwidth are presented. Bandwidth increasing is achieved by means of certain sizes choice for each reflective element so that the phase-error minimum in a required frequency range would be created . Two prototypes - single-layer and two-layer - of K-band slot reflectarray antennas have been manufactured and tested. Effectiveness of the described designing routine is proved by experimental data: achieved bandwidth for the single-layer and two-layer structure is 25% and 32% respectively.

In this paper both numerical simulation and experimental measurement of 3D-printed K-band reflectarray prototypes of closed-volume elements are performed. 3D printing technology allows designing and fabricating antenna arrays consisting of complicated-form elements. Using of closed-volume elements (air-filled hollows in a dielectric layer) enables the dielectric layer to combine functions of phase correction and protection. Some aspects of 3D-printing technology for dielectric flat lens antennas of closed-volume elements are considered.

Full-Duplex (FD) transceiver architectures have recently gained increased attention due to their potential for doubling the theoretical spectral efficiency. One of the main challenges in FD transceivers is the self-interference (SI) from the local transmitter (TX). In this paper we present a novel analog SI cancellation technique through buried-gate signaling in the fully-depleted silicon-on-insulator (FD-SOI) process. The proposed technique attenuates the TX leakage in the receiver (RX) chain before gain is applied. This relaxes the dynamic range requirement of the later RX stages by the amount of attenuation offered by the buried-gate signaling. Further, in comparison to other published analog techniques, the proposed technique offers no penalty on RX noise figure. Measured results in a 28nm FD-SOI technology demonstrate 40–50dB of SI cancellation for TX leakage as high as −10dBm, and above 20dB for TX leakage of −5dBm, with no increase in the RX noise figure.

This paper describes a digital-friendly passives-less time delay cell that generates programmable phase-shifts for down converting front-end in LO-based beamsteering receiver. Cell design supports 1.5–6.5GHz broadband receiver operation and cell layout occupies an area of only 15×16.5μm 2 including power supply rails and control logic. Simulated in 28nm CMOS technology, delay cell exhibits 6 distinct delay values {3, 3.5, 17, 19, 24, 43}ps consuming at most 220μW@IV.

This paper describes a frequency generator supporting over-an-octave tuning range for 5G receiver front-end. Generator is built by composition of smaller-range oscillators multiplexed to the common output that drives a downconversion mixer. Simulated in 28nm CMOS with full physical device models the composite oscillator exhibits a frequency tuning range from 21.5 to 60.7GHz (95.3%) dissipating less then 25.8mW from a 0.9V supply. As a result, it achieves −184dBc/Hz FOM TR.

This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with

A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the external period and reference delay is then readjusted. When on-board settling monitor observes repetition of reference delay settings, it locks delay line by applying previously collected settings. The delay line is shown to lock in presence of 30% static offset of delays from their designed values. Furthermore, random spread of delays worsened by 3 times (5% PP to 15% PP ) results in only 2% decline (3% PP to 5% PP ) after applying the proposed calibration to 16-delays line.

A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200---400 mV pp signals at date rates of 1.25---5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm2, while the actual driver occupies only 190 μm2. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below ?138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44---1.4 mW/Gbps with external clock and 2.6---4.7 mW/Gbps with clock synthesizer.

This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.

This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

In petroleum exploration, reservoir navigation is used for reaching a productive reservoir and placing the borehole optimally inside the reservoir to maximize production. For proper well placement, it is necessary to calculate in real-time parameters of the formation we are drilling in, and the parameters of formations we are approaching. Based on these results, a decision to change the direction of drilling could be made. Modern logging while drilling (LWD) extra-deep and azimuthal resistivity tools acquire multi-component, multi-spacing, and multi-frequency data that provide sufficient information for resolving the surrounding formation parameters. These tools are generally used for reservoir navigation and real-time formation evaluation. However, real-time interpretation software very often is based on simplified resistivity models that can be inadequate and lead to incorrect geosteering decisions. The core of the newly developed software is an inversion algorithm based on a model of transversely-isotropic layered earth with an arbitrary number of layers. The following model parameters are determined in real time: horizontal and vertical resistivities and thickness of each layer, formation dip, and azimuth. The inversion algorithm is based on the method of the most-probable parameter combination. The algorithm has good performance and excellent convergence due to its enhanced capability of avoiding local minima. This capability enables interpretation of real-time resistivity data, including azimuthal and extra-deep measurements. A graphical user interface was developed to provide an interactive environment for each stage of the resistivity data interpretation process: preview of input resistivity logs, initial preprocessing and filtering of raw data, creation of initial guess, running inversion and viewing inversion results, and quality control indicators. Applications of the developed software will be shown on a series of synthetic examples and field data from the North Sea. This newly developed software is currently in use for real-time reservoir navigation and post-well analysis.

openaire: EC/H2020/704947/EU//ADVANTAG5 In this article, we present a four-element Vivaldi antenna array and beamsteering receiver IC for the fifth-generation mobile network (5G) new radio (NR). The implemented receiver utilizes a delay-based local-oscillator phase shift technique for accurate beamsteering, and it exhibits 1° to 2.4° phase tuning capability for 2-5 GHz bandwidth accordingly. On-chip delay measurement is performed with pilot signal generation and delay estimation capable of 2-ps accuracy. The IC is fabricated on 28-nm CMOS technology, it occupies an area of 1.4x1.4 mm^2, including bonding pads, and consumes 22.8 mW at 2 GHz for single-receiver path operation. The receiver demonstrates wideband over-the-air reception with the prototype antennas.

This paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency. acceptedVersion