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A single transistor latch (STL), driven by impact ionization (II) and band-to-band tunneling (BTBT), plays a crucial role in threshold switching in a thin-body MOSFET. The inherent challenge lies in the high latch-up voltage ( ${V}_{\text {LU}}$ ) required to trigger the STL because the II and BTBT mechanisms rely on higher voltages. Moreover, thus far, strategies for adjusting the ${V}_{\text {LU}}$ level have been limited to altering process parameters or materials that are difficult to change once decided. Therefore, these methods do not provide dynamic controllability of ${V}_{\text {LU}}$ . The high ${V}_{\text {LU}}$ and lack of tunability limit and hinder various applications utilizing STL. In this study, ${V}_{\text {LU}}$ was experimentally reduced to near 1 V by asymmetric biasing, i.e., electrically separating the top of the body (ToB) and the bottom of the body (BoB) through front-gate (FG) biasing and back-gate (BG) biasing. The underlying physics of this reduction was elucidated by means of TCAD simulation through the analysis of energy band diagrams, II rates, and BTBT rates. A significant reduction in ${V}_{\text {LU}}$ was achieved solely through electrical modulation.

Semi-supervised learning (SSL) with pseudo-labeling is applied to the non-volatile computing-in-memory (nvCIM) architecture through weight updates of a synaptic transistor (synaptor). The synaptor is a tri-node FinFET enclosing a charge-trap layer. For on-chip training over extended periods, self-curing induced by electrothermal annealing (ETA) is utilized to raise the tunneling oxide temperature of the synaptor until it exceeds 500 °C. As a result, a classification accuracy of 86.4% is achieved by training only 1,000 labeled datasets with self-curing operations. This accuracy level is comparable to that of supervised learning (SL) with 10,000 labeled training datasets. Not only the MNIST but also the CIFAR-10 dataset was verified whether it yields similar results when using SSL.

The Schottky barrier height ( $\Phi _{\text {B}}$ ) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance ( ${R}_{\text {C}}$ ) at a Schottky junction was also analyzed by using a transmission line method (TLM). Moreover, HPDA effects on the ${R}_{\text {C}}$ were characterized on different crystal orientations of silicon, which has a different number of traps. HPDA is more effective to lower the $\Phi _{\text {B}}$ at (111) orientation than at (100) orientation because a greater number of interface traps can be passivated for an orientation with a high Miller index. Finally, a deuterium peak was physically profiled across the Schottky junction by use of time-of-flight secondary ion mass spectrometry (ToF-SIMS).