Search

We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in μm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in μm pitch. In this structure, the downward stress increases the ids of these Trs. The causes of assembly stress in pad areas are: 1) Local stress concentration to the Under Bump Metal (UBM) step at the Polyimide film (PI) aperture edge, which is induced by the contraction of the PI 2) Global stress to the solder bump, which is induced by the contraction of the Underfill resin (UF). These stresses have temperature dependence, and are relaxed between the UBM formation temperature and the glass-transition temperature (Tg) of the UF. Based on the mechanism, we propose a new structure without step in the UBM, and expect to reduce assembly stress by 30% with the new structure.

We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in µm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in µm pitch.

In a recent LSI, IR drop on power supply lines is a significant problem for high speed operation, along with an increase of power consumption. In addition, relaxing external stresses during assembly processes is also a serious issue, because more fragile low-k materials are applied to interlayer dielectric films. In this paper, we have developed new structures without adding global interconnect layers. Against the IR drop issue, we have developed 2 different structures. The first structure is the new mesh wiring structure and we have successfully reduced IR drop by 20%. The second structure is the electroless plated shunt line structure and we have successfully obtained reduction in resistance of power supply lines by 38%. To the issue of relaxing stresses, we have succeeded in reducing an assembly stress to 7% with electroless plating. These results indicate that superior structure of global layers can be realized without an increase in chip cost.