Search

We report effects for up to 100 Mrad ( ${{\rm SiO}_2}$ ) gamma-ray exposure on polycrystalline ZnO thin film transistors (TFTs) deposited by two different techniques. The radiation related TFT changes, either with or without electrical bias during irradiation, are primarily a negative ${{\rm V}_{\rm ON}}$ shift and a smaller ${{\rm V}_{\rm T}}$ shift ( $\Delta {{\rm V}_{\rm ON}}\sim - 2.5~\hbox{V}$ and $\Delta {{\rm V}_{\rm T}}\sim - 1.5~\hbox{V}$ for 100 Mrad ( ${{\rm SiO}_2}$ ) exposure). Field-effect mobility remains nearly unchanged. Both, ${{\rm V}_{\rm ON}}$ and ${{\rm V}_{\rm T}}$ shifts are nearly completely removed by annealing at $200^\circ {\rm C}$ for 1 minute and some recovery is seen even at room temperature. We find that our ZnO TFTs are insensitive to electrical bias during irradiation; that is, unbiased measurements are useful worst case test results. To the best of our knowledge, these are the most radiation-hard thin film transistors reported to date.

We report hybrid organic/inorganic complementary circuits using ink-jet-printed fluorinated 5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) as the p-channel material and zinc oxide deposited by plasma enhanced atomic layer deposition (PEALD) as the n-channel material. Using a mixed solvent system, discrete ink-jet printed diF-TESADT OTFTs have field effect mobility as large as 0.4 cm2/V s. PEALD ZnO TFTs typically have field-effect mobility >15 cm2/V s. Using p-type diF-TESADT and n-type ZnO active layers in a simple, 4-mask, 1 ink jet printing step, low temperature ( ⩽ 200 ° C process we fabricated complimentary MOS (CMOS) inverters with maximum voltage gain of 35 and sub-pA leakage currents for both low and high input levels.

We have fabricated ZnO thin film transistors (TFTs) on rigid and flexible substrates with characteristics well suited for displays and more general microelectronic applications. Using weak-reactant plasma enhanced atomic layer deposition (PEALD) we have fabricated single-gate, double-gate, and trilayer ZnO TFTs with good performance and stability. We have also fabricated TFTs and circuits on thin (few μm thick) solution-cast polymeric substrates that can be flexed to small radius for thousands of cycles.

In this letter, we report trilayer ZnO thin-film transistors (TFTs) with in situ Al2O3 passivation fabricated using plasma-enhanced atomic layer deposition. The bottom-gate, top-contact TFTs use an Al2O3-ZnO-Al2O3 trilayer deposited in one deposition run at 200°C that provides protection for the active layer back surface with no extra passivation step. Compared with Al2O3 passivated, nontrilayer ZnO TFTs, these trilayer devices have similar field effect mobility, but more positive turn-on voltage and improved bias stability. Seven-stage trilayer ZnO TFT ring oscillators operated at 3.5 MHz at a supply voltage of 17 V, corresponding to a propagation delay of ~ 27 ns/stage.

In this letter, we report double-gate ZnO thin-film transistor (TFT) circuits deposited by plasma-enhanced atomic layer deposition that are suitable for low-voltage operation. Compared to bottom-gate-only ZnO TFTs, double-gate ZnO TFTs have improved mobility, subthreshold slope, and bias stability. In this letter, the TFT top gate is used to adjust the bottom-gate turn-on and threshold voltage. This allows the logic transition point for circuits to be adjusted for operation at a low voltage. Using this approach, high-gain inverters (gain >100) and low-voltage ring oscillators using double-gate TFTs have been demonstrated. Double-gate inverters with a beta ratio of 5 have a gain larger than 100. Fifteen-stage double-gate ZnO TFT ring oscillators operate with VDD = 1.5 V, ID = 28 μA, and propagation delay of 2 μs per stage.

We describe pH-controlled selective etching of atomic layer deposition (ALD) Al2O3 over ZnO. Film thickness as a function of etch exposure was measured by spectroscopic ellipsometry. We find that alkaline aqueous solutions with pH between about 9 and 12 will etch Al2O3 at useful rate with minimal attack of ZnO. Highly selective etching of Al2O3 over ZnO (selectivity >400:1) and an Al2O3 etch rate of ∼50 nm/min can be obtained using a pH 12 etch solution at 60 °C.

Radiation tolerance is of interest in electronic applications such as radiation sensors, nuclear reactors, x-ray imagers, and high-energy particle accelerators. While properly designed Si MOSFETS are usefully radiation resistant, most thin-film transistors (TFTs), including polysilicon and a-Si:H, are severely degraded by relatively low irradiation dose (typically

Radial junction Si pillar array solar cells based on the heterojunction with intrinsic thin layer (HIT) structure were fabricated from p-type crystal Si (c-Si) wafers of different doping densities. The HIT structure consisting of intrinsic/n-type hydrogenated amorphous Si (a-Si:H) deposited by plasma-enhanced chemical vapor deposition (PECVD) at low temperature (200°C) was found to effectively passivate the high surface area of the p-type Si pillar arrays resulting in open circuit voltages (Voc>0.5) comparable to that obtained on planar devices. At high c-Si doping densities (>1018 cm-3), the short-circuit current density (Jsc) and energy conversion efficiency of the radial junction devices were higher than those of the planar devices demonstrating improved carrier collection in the radial junction structure.

In oxide semiconductors, defect chemistry and hydrogen can influence free carrier concentration and these materials can have strong interactions with the atmosphere and contaminents.[1,2] An inverted staggered structure is commonly used for oxide TFTs and a high-quality passivation layer is needed to provide protection and minimize back channel surface charge changes.[2,3] Negative shifts in turn-on and threshold voltage after passivation with inorganic thin films have been reported by several groups.[4,5] We have previously reported weak oxidant plasma enhanced atomic layer deposition (PEALD) ZnO TFTs with an ALD-based Al2O3 passivation layer [6]. Before passivation the TFT has a turn-on voltage near 0 V, but significant hysteresis (often > 0.5 V). A 32 nm thick Al2O3 layer deposited by ALD eliminates the hysteresis, but causes a negative shift in turn-on and threshold voltage (~3 V). A 32 nm thick Al2O3 layer deposited by PEALD also removes the hysteresis, but shifts the device turn-on and threshold voltage negative by more than 10 V [6]. We have developed a tri-layer process for bottom-gate, top contact TFTs. An Al2O3-ZnO-Al2O3 tri-layer is deposited sequentially at 200°C and provides effective passivation and reduced turn-on voltage shift.

We report here double-gate ZnO thin film transistor (TFT) circuits with operation at low voltage. TFTs with low voltage operation have been reported previously, but often use very thin (few nm thick) gate dielectric which may limit manufacturability [1]. Oxide semiconductor-based TFTs have been extensively studied as competitive candidates for next-generation display technology and other large-area electronics. For many applications, operation at voltages compatible with low-voltage CMOS is important. Double-gate TFTs are of interest because they allow threshold voltage tuning, improved device performance, and circuit applications like mixers. [2,3] We have previously reported bottom-gate ZnO TFTs and circuits fabricated on glass and flexible polymeric substrates using plasma enhanced atomic layer deposition (PEALD) [4,5]. Here we report double-gate ZnO TFTs and circuits fabricated on glass substrates using PEALD with a maximum process temperature of 200 °C. Compared to bottom-gate ZnO TFTs, double-gate ZnO TFTs have higher mobility, and reduced substhreshold slope. In these devices, the top gate can be used to vary the bottom-gate threshold voltage by more than 4 V. This allows the logic transition point for circuits to be adjusted as desired and allows logic operation at low voltage. 15 stage double-gate ZnO TFT ring oscillators operate well with V DD = 1.2 V, I D = 32 µA, and propagation delay of 2.1 µs/stage.

Oxide semiconductor TFTs are of interest where low-cost, high mobility, and compatibility with flexible substrates is required. We have previously demonstrated high quality thin-film transistors (TFTs) using ZnO and Al 2 O 3 deposited at low temperature (200°C) by weak oxidant, plasma-enhanced atomic layer deposition (PEALD) using a reactor utilizing a pump and purge mode of operation [1]. We also reported the use of thin, weak oxidant, PEALD Al 2 O 3 films as gate insulator for scaled III-V MOSFETs [2]. In this work, we report TFTs fabricated using ZnO and Al 2 O 3 deposited in a novel weak oxidant PEALD reactor using a showerhead to dispense the reactant gases and an integrated load-lock.

We report double-gate ZnO thin film transistors fabricated using weak reactant plasma enhanced atomic layer deposition (PEALD) with a maximum process temperature of 200˚C. When operated as bottom gate only devices the TFTs have linear region mobility of 19 cm2/V⋅s and the top gate can be used to vary the bottom-gate TFT threshold voltage by more than 2 V. With top and bottom gates connected together the linear region mobility increases to 24 cm2/V⋅s, with a subthreshold slope of 160 mV/decade. The low process temperature of these devices allows simple fabrication on polyimide and other flexible polymeric substrates. Double gate TFTs are of interest to allow threshold voltage tuning, improved device performance and stability, and for circuit applications like mixers and analog circuits design. Double gate TFTs have been demonstrated using GIZO[1, 2]; however, these reports used a maximum process temperature of 350 °C, too high for flexible polymeric substrates. We have previously reported high quality ZnO TFTs fabricated on both glass and plastic substrates using weak reactant PEALD with a maximum process temperature of 200 °C[3, 4]. We now report double gate TFTs with the same maximum process temperature.

We developed an implantable thin film transistor temperature sensor (TFT-TS) to measure temperature changes in the brain. These changes are assumed to be associated with cerebral metabolism and neuronal activity. Two prototype TFT-TSs were designed and tested in-vitro: one with 8 diode-connected single-ended sensors, and the other with 4 pairs of differential-ended sensors in an array configuration. The sensor elements are 25 ~ 100 pm in width and 5 μm in length. The TFT-TSs were fabricated based on high-speed ZnO TFT process technology on flexible polyimide substrates (50 μm thick, 500 μm width, 20 mm length). In order to interface external signal electronics, they were directly bonded to a prototype printed circuit board using anisotropic conductive films The prototypes were characterized between 23 ~ 38 °C using a commercial temperature sensor and custom-designed temperature controlled oven. The maximum sensitivity of 40 mV/°C was obtained from the TFT-TS.

Oxide semiconductor electronics may enable new applications including large-area, flexible, integrated systems. ZnO thin film transistors have been reported with field-effect mobility > 100 cm2/V·s, on-current density > 700 mA/mm, and microwave operation (f T > 2 GHz, f max > 7 GHz) for ZnO deposited by pulsed laser deposition at 400°C.[1] Other oxide semiconductors, including amorphous and crystalline mixtures of I 2 O 3 , Ga 2 O 3 , ZnO, have also been widely studied, and high mobility (> 30 cm2/V·s) thin film transistors and circuits with propagation delays d = dI DS /dV DS ) observed in a range of oxide thin film transistors. In particular we find that self-heating is a significant limiting factor for the performance of oxide devices and circuits on low-cost, low-thermal conductivity substrates such as glass and plastic.

We report using a novel weak-oxidant plasma-enhanced atomic layer deposition (PEALD) process at 200 °C to deposit ZnO thin films for stable, high mobility, pyroelectric thin film transistors (TFTs). Our PEALD ZnO TFTs use Al 2 O 3 gate dielectric, also deposited by PEALD, and have field-effect mobility of 20–30 cm2/V⋅s. In these ZnO TFTs the mobility is found to be very weakly temperature activated (< 10 meV) down to 77 K, but the devices have a fast, linear, and reversible, threshold voltage shift with temperature which is believed to be related to pyroelectric charge in the ZnO layer.

The demand for low-cost, high mobility, thin-film technologies has generated particular interest in low-temperature- processed organic and metal oxide semiconductors. In addition, the development of CMOS circuits is likely to be important for low-power and battery-driven technologies. We have focused on ZnO, one of the most promising n- type semiconductors for thin-film application, but to date the formation of stable, high-mobility p-type at low temperatures has been challenging. We have previously demonstrated that by using a low-temperature (200degC) atmospheric pressure spatial ALD process, we can deposit uniform A1203 and ZnO films that result in high-mobility transistors (>15 cm2/V-s) and fast ring oscillators (

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

— The impact of passivation processes on ZnO thin-film transistors is reported. In general, passivation processes result in back-channel doping, which corresponds to shifts in threshold voltage and changes in subthreshold slope. It was determined that ALD-based passivation results in considerably smaller undesirable shifts than those observed with plasma-based processes. Two approaches, one a bulk doping with ammonia and the other a surface treatment with hydrogen peroxide, to further mitigate the detrimental effects of the passivation process are described. After proper passivation, ZnO devices show negligible hysteresis, have excellent stability to bias stress, and maintain or improve the good transport properties of as-deposited devices. Although the existence of grain boundaries has been assumed to be a point of concern for device stability in polycrystalline metal oxides, no evidence was found to suggest that the grain boundaries present in these ZnO thin-film transistors have affected the device stability.

We report using a novel, weak oxidant, plasma-enhanced atomic layer deposition (PEALD) process at 200 °C to fabricate stable, high mobility ZnO thin film transistors (TFTs) and fast circuits on glass and polyimide substrates. Weak oxidant PEALD provides a simple, fast deposition process that results in uniform, conformai semiconductor and dielectric layers and enhancement-mode MOSFETs from uncompensated films. Highly conformai PEALD Al2O3 layers provide a high yield dielectric on rough plastic substrates for both PEALD ZnO TFTs and cross-overs. Our PEALD ZnO TFTs have field-effect mobility of >20 cm2/V·s on polyimide substrates with excellent bias stress stability. TFTs biased continuously for 40,000s showed