33 results on '"Yu-Ching Tsao"'
Search Results
2. Improving Breakdown Voltage in AlGaN/GaN Metal-Insulator-Semiconductor HEMTs Through Electric-Field Dispersion Layer Material Selection
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Yun-Hsuan Lin, Jen-Wei Huang, Hong-Yi Tu, Pei-Yu Wu, Mao-Chou Tai, Yu-Ching Tsao, Yu-Shan Lin, Ya-Ting Chien, Ting-Chang Chang, Fong-Min Ciou, Hao-Xuan Zheng, Fu-Yuan Jin, and Yu-Lin Tsai
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Materials science ,business.industry ,Wide-bandgap semiconductor ,Dielectric ,Electronic, Optical and Magnetic Materials ,Stress (mechanics) ,Semiconductor ,Electric field ,Dispersion (optics) ,Breakdown voltage ,Optoelectronics ,Electrical and Electronic Engineering ,Safety, Risk, Reliability and Quality ,business ,Voltage - Abstract
In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ( $\text{I}_{\mathrm{ on}}$ ) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device.
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- 2021
3. Vertical Electric Field-Induced Abnormal Capacitance–Voltage Electrical Characteristics in a-InGaZnO TFTs
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Jian-Jie Chen, Jen-Wei Huang, Ting-Chang Chang, Wen-Chi Wu, Yong-Ci Zhang, Chih-Chih Lin, Hsin-Chieh Li, Kuan-Ju Zhou, Chuan-Wei Kuo, Yu-Ching Tsao, Hong-Chih Chen, and Tsung-Ming Tsai
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Electrolysis ,Materials science ,Condensed matter physics ,Instability ,Capacitance ,Electronic, Optical and Magnetic Materials ,law.invention ,Stress (mechanics) ,Capacitance voltage ,Thin-film transistor ,law ,Electric field ,Electrode ,Electrical and Electronic Engineering - Abstract
This study investigates an abnormal degradation induced in a moist environment. Although devices maintain optimal performance under bias stress operation in a vacuum, an abnormal hump is observed in capacitance–voltage ( ${C}$ – ${V}$ ) electrical characteristics under negative bias stress (NBS) operation in a moist environment. Electrolysis of the H2O model is proposed to explain the degradation. An asymmetric stress condition, with ${V} _{\text {GD}} = {0}$ V, is designed to confirm that a vertical electric field causes the electrolysis of H2O, which is the reason for the hump phenomenon in the ${C}$ – ${V}$ curve. Moreover, COMSOL simulation and ${C}$ – ${V}$ measurement of the source and drain parasitic capacitances are utilized to clarify the precise degradation position and support the mechanism. The results from electrical measurement suggest that a vertical electric field can cause instability in a moist environment.
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- 2021
4. On the Optimization of Performance and Reliability in a-InGaZnO Thin-Film Transistors by Versatile Light Shielding Design
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Simon M. Sze, Yu-Chieh Chien, Ya-Ting Chien, Hong-Yi Tu, Jian-Jie Chen, Yu-Ching Tsao, Chuan-Wei Kuo, Yu-Lin Tsai, Tsung-Ming Tsai, Hong-Chih Chen, and Ting-Chang Chang
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010302 applied physics ,Materials science ,business.industry ,Transistor ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Amorphous solid ,Stress (mechanics) ,Parasitic capacitance ,law ,Thin-film transistor ,Logic gate ,0103 physical sciences ,Electromagnetic shielding ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Layer (electronics) - Abstract
This work studies the effect of the location of the light shielding (LS) layer on negative bias illumination stress (NBIS) instability in self-aligned top-gate amorphous indium-gallium-zinc oxide thin-film transistors (SA-TG a-InGaZnO TFTs). Although the NBIS instability can be mitigated by introducing a fully covered LS layer, it causes an unwanted parasitic capacitance, as evidenced by capacitance–voltage ( ${C}$ – ${V}$ ) measurements. An alternative solution, in which the device that is partially covered by the LS layer at the source side, is proposed to optimize the tradeoff. This study suggests that an LS layer could be adopted in the SA-TG configuration, as it is versatile in different structural designs, depending on the requirement of targeted applications.
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- 2021
5. A Novel Ultrawideband Absorptive Common-Mode Filter Design Using a Miniaturized and Resistive Defected Ground Structure
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Yih-Peng Chiou, Shi-Kang Tseng, Yu-Ching Tsao, and Cheng-Nan Chiu
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Materials science ,Bandwidth (signal processing) ,020206 networking & telecommunications ,02 engineering and technology ,Stopband ,Condensed Matter Physics ,Noise (electronics) ,Atomic and Molecular Physics, and Optics ,law.invention ,Filter design ,Filter (video) ,law ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Equivalent circuit ,Signal integrity ,Electrical and Electronic Engineering ,Resistor - Abstract
An ultrawideband absorptive common-mode filter (A-CMF) with a newly developed defected ground structure (DGS) is proposed in this article. The DGS miniaturized to a subwavelength size is able to totally suppress the common-mode noise while maintaining the signal integrity of the differential mode. In addition, the reflection and radiation of the common-mode noise are negligible in the stopband. For quick design, a simplified equivalent circuit model is also proposed. This model can be employed to estimate the resistances of the lumped resistors embedded in the DGS to obtain a very wide absorption band. In the demonstrated example, the fractional bandwidth determined by a 90% absorption efficiency can achieve as large as 104% around 3.55 GHz for an A-CMF realized on a simple two-layer printed circuit board. Such a widely absorptive bandwidth is never achieved before to our knowledge. The design methodology is validated by full-wave simulation. Finally, real measurement of the design is also carried out to confirm the design and analysis.
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- 2021
6. Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors
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Shin-Ping Huang, Po-Hsun Chen, Guan-Fu Chen, Ting-Chang Chang, Hui-Chun Huang, Wei-Chih Lai, Yang-Hao Hung, Jian-Jie Chen, Yu-Ching Tsao, An-Kuo Chu, Hong-Chih Chen, Kuan-Ju Zhou, and Chuan-Wei Kuo
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010302 applied physics ,Materials science ,business.industry ,Transistor ,Gate dielectric ,Dielectric ,Thermal conduction ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Stress (mechanics) ,law ,Thin-film transistor ,Electric field ,Logic gate ,0103 physical sciences ,Optoelectronics ,Electrical and Electronic Engineering ,business - Abstract
This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.
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- 2019
7. Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes
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Yu-Zhe Zheng, Mao-Chou Tai, Yu-Lin Tsai, Hong-Yi Tu, Yu-Ching Tsao, Shin-Ping Huang, Yu-Xuan Wang, Tsung-Ming Tsai, Chia-Chuan Wu, Ting-Chang Chang, and Hong-Chih Chen
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010302 applied physics ,Negative-bias temperature instability ,Materials science ,Condensed matter physics ,Hydrogen ,Low-temperature polycrystalline silicon ,Dangling bond ,chemistry.chemical_element ,01 natural sciences ,Grain size ,Electronic, Optical and Magnetic Materials ,Stress (mechanics) ,chemistry ,Thin-film transistor ,0103 physical sciences ,Grain boundary ,Electrical and Electronic Engineering - Abstract
This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.
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- 2019
8. Abnormal Back Channel Leakage Under Large Drain Voltage in Short Channel Organic Thin-Film Transistors
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Jian-Jie Chen, Yao-Chih Chuang, Shengdong Zhang, Wan-Ching Su, Ting-Chang Chang, Shin-Ping Huang, Hong-Chih Chen, Yu-Ching Tsao, Kuan-Ju Zhou, Chuan-Wei Kuo, Guan-Fu Chen, Ming-Chang Yu, and Sung-Chun Lin
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010302 applied physics ,Materials science ,business.industry ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Organic semiconductor ,law ,Thin-film transistor ,Logic gate ,0103 physical sciences ,Electrode ,Hardware_INTEGRATEDCIRCUITS ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Hardware_LOGICDESIGN ,Communication channel ,Leakage (electronics) ,Voltage - Abstract
This study investigates short channel (length $ ) p-type organic thin-film transistor (OTFT) devices which exhibit off-state leakage in their ID–VG characteristics. This phenomenon is attributed to the fact that when a lower positive gate voltage is applied, gate voltage cannot control the back channel, causing back channel leakage. The behavior of back channel leakage is confirmed by the OTFT saturated-regime drain-current formula multiplied by channel length. For dual gate OTFT devices, a top gate voltage sweep and fixed different bottom gate voltages are applied, which indicates that the conduction path is distributed throughout the entire organic semiconductor (OSC) layer, and the back channel leakage can be suppressed by a positive bottom gate voltage. Finally, using dual gate sweeping for a dual gate OTFT device allows the top and bottom gate voltage to simultaneously control the front and back channels, causing a suppression of the back channel leakage, an improvement in subthreshold swing (SS) from 420 to 200 (mV/decade) and an on current increase from $\textsf {7.8}\times \textsf {10}^{-\textsf {8}}$ to $\textsf {3.3}\times \textsf {10}^{-\textsf {7}}$ A at VG-Vsub-threshold = −8 V for the W/L $=50/20~\mu \text{m}$ device.
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- 2019
9. Abnormal ${C}$ –${V}$ Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs
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Yu-Zhe Zheng, Terry Tai-Jui Wang, Po-Hsun Chen, Yu-Ching Tsao, Hong-Chih Chen, Ann-Kuo Chu, Wei-Han Chen, Shin-Ping Huang, Yu-Xuan Wang, Yu-Hua Chung, Chia-Chuan Wu, Shengdong Zhang, Yu-Shan Shih, Yao-Kai Shih, and Ting-Chang Chang
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010302 applied physics ,Materials science ,Condensed matter physics ,Transistor ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Threshold voltage ,Thin-film transistor ,law ,Electric field ,Logic gate ,0103 physical sciences ,Trapping region ,Electrical and Electronic Engineering ,Quantum tunnelling ,Leakage (electronics) - Abstract
We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.
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- 2019
10. Impact of Dehydrogenation Annealing Process Temperature on Reliability of Polycrystalline Silicon Thin Film Transistors
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Yu-Zhe Zheng, Po-Hsun Chen, Ting-Chang Chang, Yu-Shan Shih, Yu-Ching Tsao, Shin-Ping Huang, Hong-Chih Chen, Yu-Xuan Wang, Wei-Chih Lai, Chia-Chuan Wu, and Ann-Kuo Chu
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010302 applied physics ,Negative-bias temperature instability ,Materials science ,Silicon ,business.industry ,Annealing (metallurgy) ,Dangling bond ,chemistry.chemical_element ,engineering.material ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Polycrystalline silicon ,chemistry ,Thin-film transistor ,0103 physical sciences ,Density of states ,engineering ,Optoelectronics ,Electrical and Electronic Engineering ,business - Abstract
This letter investigates variations in polycrystalline silicon thin film transistor (TFT) performance under illumination and negative bias temperature instability (NBTI) tests due to different dehydrogenation annealing temperatures during the fabrication process. The depth of the density of state (DOS) in polysilicon can be indirectly determined by the TFT response to light illumination, since dangling bonds act as recombination centers. The electrical characteristics of TFTs after undergoing NBTI can also be indicative of the bonding type of silicon atoms. By analyzing the results of these reliability tests, the type of DOS can be clarified, which is beneficial for realizing the relationship between performance and reliability.
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- 2019
11. Improving Reliability of High-Performance Ultraviolet Sensor in a-InGaZnO Thin-Film Transistors
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Yu-Shan Shih, Yu-Lin Tsai, Hui-Chun Huang, Hong-Yi Tu, Yu-Ching Tsao, Kuan-Ju Zhou, Yu-Xuan Wang, Mao-Chou Tai, Ting-Chang Chang, I-Nien Lu, Yu-Chieh Chien, and Jian-Jie Chen
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010302 applied physics ,Materials science ,business.industry ,Transistor ,medicine.disease_cause ,01 natural sciences ,Capacitance ,Electronic, Optical and Magnetic Materials ,law.invention ,law ,Thin-film transistor ,Electric field ,Logic gate ,0103 physical sciences ,Band diagram ,medicine ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Technology CAD ,Ultraviolet - Abstract
High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.
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- 2019
12. A Novel Heat Dissipation Structure for Inhibiting Hydrogen Diffusion in Top-Gate a-InGaZnO TFTs
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Ting-Chang Chang, Hui-Chun Huang, Hong-Chih Chen, Kuan-Ju Zhou, Chuan-Wei Kuo, An-Kuo Chu, Yu-Ching Tsao, Wei-Chih Lai, Shin-Ping Huang, Po-Hsun Chen, Guan-Fu Chen, and Jian-Jie Chen
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Materials science ,Hydrogen ,business.industry ,Transistor ,chemistry.chemical_element ,Electronic, Optical and Magnetic Materials ,law.invention ,Threshold voltage ,Stress (mechanics) ,chemistry ,law ,Optoelectronics ,Degradation (geology) ,Electrical and Electronic Engineering ,Current (fluid) ,Diffusion (business) ,business ,Joule heating - Abstract
In order to better understand the reliability issues in top-gate a-InGaZnO (a-IGZO) thin-film transistors, this letter investigates the degradation mechanism of a device under self-heating stress (SHS). After applying hot carrier stress, a negative threshold voltage ( ${V} _{\text {TH}}$ ) shift, a hump effect, and normally- ON current degradation were found. COMSOL simulation results of hydrogen diffusion in the source and drain (n+ region) of a-IGZO show that Joule heat was generated in the channel during SHS, which leads to hydrogen diffusion in the central and side channels. The unequal channel thermal effect results in a hump effect in the electrical characteristics, and the self-heating effect becomes more prominent as the channel width increases. To minimize the effects of these abnormal phenomena under high current operation in future display applications, a method of creating structural divisions in the channel width is used to aid overall heat dissipation and reduce the effect of SHS degradation.
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- 2019
13. Abnormal Unsaturated Output Characteristics In a-InGaZnO TFTs With Light Shielding Layer
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Mao-Chou Tai, Wei-Chih Lai, Ting-Chang Chang, Po-Hsun Chen, Shin-Ping Huang, Yu-Ching Tsao, Kuan-Ju Zhou, Chuan-Wei Kuo, Hong-Chih Chen, Guan-Fu Chen, Jian-Jie Chen, and An-Kuo Chu
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010302 applied physics ,Capacitive coupling ,Materials science ,Condensed matter physics ,Transistor ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Threshold voltage ,law ,Thin-film transistor ,Electric field ,0103 physical sciences ,Electromagnetic shielding ,Electric potential ,Electrical and Electronic Engineering ,Voltage - Abstract
In this letter, we integrated a floating bottom gate (BG) as a light shielding layer in a thin-film transistor (TFT). We observed abnormal ${I}_{D}$ – ${V}_{D}$ output characteristics and unsaturated current characteristics. In addition, drain-induced barrier lowering has a significant impact on ${I}_{D}$ – ${V}_{D}$ characteristics as the drain voltage increases. These phenomena are due to changes in electrical potential that occur due to the capacitive coupling effect. Technology computer aided design simulations explained and correlated well with our observations. Then, a physical model is proposed to verify the abnormal electrical characteristics. Grounding the BG light shield was found to provide better control over the threshold voltage and total current performance. This letter results may lead to better applications in the TFT driving circuits.
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- 2019
14. Hydrogen as a Cause of Abnormal Subchannel Formation Under Positive Bias Temperature Stress in a-InGaZnO Thin-Film Transistors
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Tsung-Ming Tsai, Mao-Chou Tai, Yu-Chieh Chien, Yu-Lin Tsai, Yi-Chieh Yang, Po-Hsun Chen, Yu-Ching Tsao, Hsiao-Cheng Chiang, and Ting-Chang Chang
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010302 applied physics ,Materials science ,Hydrogen ,Condensed matter physics ,Annealing (metallurgy) ,chemistry.chemical_element ,01 natural sciences ,Temperature stress ,Instability ,Temperature measurement ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,chemistry ,Thin-film transistor ,0103 physical sciences ,Positive bias ,Electrical and Electronic Engineering - Abstract
This paper analyzes the abnormal degradation induced by hydrogen annealing. Although device performance is enhanced after hydrogen annealing, an abnormal hump is observed in transfer characteristics ( ${I}_{D} - {V}_{G}$ ) under positive bias temperature stress (PBTS). Threshold voltage shift ( $\Delta \text{V}_{\text {TH2}}$ ) in this hump region increases with increasing stress voltage and temperature. Additionally, $\Delta \text{V}_{\text {TH2}}$ is independent of the channel width. A novel hydrogen rupture-diffusion model is proposed to explain the degradation. COMSOL simulation and ${C} - {V}$ measurement are utilized to clarify the precise degradation position. Moreover, variable S/D spacing ( $\text{L}_{\text {SD}}$ ) devices are designed to support the mechanism. Finally, ISE-TCAD software is carried out to verify the proposed model. Our results from electrical measurement suggest that hydrogen can cause additional instability, which shares a similar conclusion for those by using material analyzation and first-principle simulation.
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- 2019
15. Reliability Test Integrating Electrical and Mechanical Stress at High Temperature for a-InGaZnO Thin Film Transistors
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Yu-Lin Tsai, Shin-Ping Huang, Yu-Chieh Chien, Ting-Chang Chang, Hong-Yi Tu, Yu-Ching Tsao, Jen-Wei Huang, and Mao-Chou Tai
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010302 applied physics ,Materials science ,Subthreshold conduction ,Transistor ,Bending ,01 natural sciences ,Temperature measurement ,Electronic, Optical and Magnetic Materials ,law.invention ,Stress (mechanics) ,Compressive strength ,law ,Etching (microfabrication) ,Thin-film transistor ,0103 physical sciences ,Electrical and Electronic Engineering ,Composite material ,Safety, Risk, Reliability and Quality - Abstract
This paper demonstrates the cumulative effects of compressive stress and high current stress at high temperature in flexible a-InGaZnO4 thin-film transistors. An abnormal hump can be found in the subthreshold regime in the results from a reliability test that combines high temperature and high current stress with mechanical bending at 10 mm. During this stress, holes will tend to inject into the defects in the etching stop layer near the source side, which is induced by compressive bending. A COMSOL simulation was performed and confirmed that defect generation occurs in the etching stop layer during compressive bending. Further, the path of the back-channel leakage current caused by the localized trapped holes was also confirmed by changing the width/length of thin film transistors (TFTs) in the reliability test. The precise hole trapping distribution was verified by a single side capacitance-voltage measurement and source/drain interchange measurement.
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- 2019
16. Effect of Different a-InGaZnO TFTs' Channel Thickness upon Self-Heating Stress
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Chih-Chih Lin, Yu-Lin Tsai, Hong-Yi Tu, Yu-Ching Tsao, Jian-Jie Chen, Mao-Chou Tai, Po-Wen Chang, Ting-Chang Chang, and Yu-Xuan Wang
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Stress (mechanics) ,Materials science ,business.industry ,Optoelectronics ,business ,Self heating ,Communication channel - Published
- 2019
17. Effects of Ultraviolet Light on the Dual-Sweep <tex-math notation='LaTeX'>$I$ </tex-math> – <tex-math notation='LaTeX'>$V$ </tex-math> Curve of a-InGaZnO4 Thin-Film Transistor
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Hong-Yi Tu, Shengdong Zhang, Yu-Ching Tsao, Ting-Chang Chang, Yu-Lin Tsai, Jen-Wei Huang, Mao-Chou Tai, Shin-Ping Huang, and Hong-Chih Chen
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010302 applied physics ,Materials science ,business.industry ,Transistor ,medicine.disease_cause ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Amorphous solid ,Threshold voltage ,Thin-film transistor ,law ,Logic gate ,0103 physical sciences ,Electrode ,medicine ,Ultraviolet light ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Ultraviolet - Abstract
The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.
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- 2019
18. Effect of a-InGaZnO TFT Channel Thickness under Self-Heating Stress
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Jian-Jie Chen, Yu-Lin Tsai, Chih-Chih Lin, Yu-Xuan Wang, Mao-Chou Tai, Ting-Chang Chang, Po-Wen Chang, Hong-Yi Tu, and Yu-Ching Tsao
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Stress (mechanics) ,Materials science ,Thin-film transistor ,business.industry ,Optoelectronics ,Self heating ,business ,Electronic, Optical and Magnetic Materials ,Communication channel - Published
- 2019
19. Modified Conductance Method for The Extraction of Interface Traps in GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors
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Ting-Tzu Kuo, Yu-Chieh Chien, Yu-Ching Tsao, Yu-Shan Lin, Po-Hsun Chen, Ting-Chang Chang, and Fong-Min Ciou
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010302 applied physics ,Materials science ,business.industry ,Transistor ,Wide-bandgap semiconductor ,Conductance ,Gallium nitride ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Capacitance ,law.invention ,chemistry.chemical_compound ,Semiconductor ,chemistry ,Silicon nitride ,law ,0103 physical sciences ,Optoelectronics ,Equivalent circuit ,0210 nano-technology ,business - Abstract
This work demonstrates a modified conductance method for the characterization of interface traps in gallium-nitride metal-insulator-semiconductor high electron mobility transistors. It is observed that the defect states cannot be extracted by conventional conductance method in which the capacitance of insulator layer, for instance silicon nitride, is typically selected as the oxide capacitance for conductance calculation. Although the origin remains unclear, it is likely due to the additional effect from aluminum gallium nitride blocking layer that significantly affects the extraction results. A modified equivalent circuit model is proposed accordingly to solve this issue. Additionally, temperature-dependent measurement is carried out to probe the interface traps under different energy levels by our proposed technique.
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- 2020
20. Obtaining impact ionization-induced hole current by electrical measurements in gallium nitride metal–insulator–semiconductor high electron mobility transistors
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Yu-Hsuan Yeh, Ting-Chang Chang, Hao-Xuan Zheng, Fong-Min Ciou, Li-Chuan Sun, Kuan-Hsu Chen, Wei-Chen Huang, Yu-Ching Tsao, Yu-Shan Lin, Kuan-Ju Zhou, Jen-Wei Huang, and Yung-Fang Tan
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Materials science ,Acoustics and Ultrasonics ,Gallium nitride ,02 engineering and technology ,01 natural sciences ,law.invention ,Ion ,chemistry.chemical_compound ,Reliability (semiconductor) ,law ,0103 physical sciences ,Electrical measurements ,010302 applied physics ,business.industry ,Transistor ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Impact ionization ,Semiconductor ,chemistry ,Optoelectronics ,0210 nano-technology ,business - Abstract
In this paper, an extraction method for measuring impact ionization-induced hole current in gallium nitride (GaN) metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) is proposed. The results show that the non-monotonic impact ionization current characteristic can be easily acquired by the extraction method. Further, different hot-carrier stress (HCS) conditions can be obtained based on the I G–V G curve, and the reliability tests can act as verification of the impact-ionization curve. In addition, electrical reliability tests indicate that the threshold voltage (V TH) shift and on-state current (I on) degradation in the MIS-HEMTs have a positive correlation to impact ionization-generated hole current. During HCS operation, the V TH will shift positively and I on decreases due to hot electrons trapping into the GaN layer. This model is validated by TCAD simulation.
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- 2021
21. Systematic Analysis of High-Current Effects in Flexible Polycrystalline-Silicon Transistors Fabricated on Polyimide
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Yu-Ho Lin, Li-Hui Chen, Hsiao-Cheng Chiang, Hsueh-Hsing Lu, Yu-Ju Hung, Kuan-Chang Chang, Wan-Ching Su, Ting-Chang Chang, Jianwen Yang, Hung Wei Li, Ann-Kuo Chu, Hsin-Lu Chen, Bo-Wei Chen, Chih-Hung Tsai, Shin-Ping Huang, Tai-Fa Young, Po-Yung Liao, Yu-Ching Tsao, and Yu-Zhe Zheng
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010302 applied physics ,Fabrication ,Materials science ,business.industry ,Transistor ,02 engineering and technology ,engineering.material ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Stress (mechanics) ,Polycrystalline silicon ,law ,Thin-film transistor ,Logic gate ,0103 physical sciences ,Electronic engineering ,engineering ,Optoelectronics ,Electrical and Electronic Engineering ,0210 nano-technology ,business ,Layer (electronics) ,Polyimide - Abstract
This paper systematically studies high-current-induced effects, hot-carrier effects, and self-heating effects in flexible low-temperature polycrystalline-silicon thin-film transistors fabricated on polyimide. By utilizing ${I}$ – ${V}$ and various-frequency ${C}$ – ${V}$ measurements, the exact location of defects generated by the self-heating effects can be clarified. The degradation mechanism is found to originate from asymmetric negative-bias temperature instability. After clarifying this mechanism, the self-heating effects were shown to be alleviated by manipulating the fabrication of the buffer layer, thereby improving heat dissipation capabilities.
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- 2017
22. Role of H2O Molecules in Passivation Layer of a-InGaZnO Thin Film Transistors
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Shih Chih-Cheng, Tsung-Ming Tsai, Yu-Ching Tsao, Kuan-Chang Chang, Ting-Yang Chu, Yu-Chieh Chien, Po-Yung Liao, Ting-Chang Chang, Yu-Ju Hung, Bo-Wei Chen, Yi-Chieh Yang, Chiang Hsiao-Cheng, and Hua-Mao Chen
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010302 applied physics ,Materials science ,Hydrogen ,Passivation ,Condensed matter physics ,Doping ,Oxide ,chemistry.chemical_element ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Amorphous solid ,chemistry.chemical_compound ,chemistry ,Thin-film transistor ,0103 physical sciences ,Electronic engineering ,Electrical and Electronic Engineering ,0210 nano-technology ,Saturation (magnetic) - Abstract
This letter analyzes performance and reliability of inverted staggered type amorphous indium–gallium–zinc oxide devices in a moist environment with H2O molecules in the passivation layer. There is a negative threshold voltage shift ( $\vartriangle ~\text{V}_{\mathrm {{th}}}$ ) in the saturation region (VD = 10 V), which increases with decreasing channel length. We propose that this is explained by the drain-induced barrier lowering that is due to the H2O molecules. Moreover, a hydrogen bonding model under bias stress is also proposed, in contrast to the conventional H2O doping model. Recovery behavior after bias stress and ac operation were utilized to distinguish the difference between these models.
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- 2017
23. Contradiction Behaviors between I-V and C-V Curves after Self-Heating Stress in a-IGZO TFT with Triple-Stacked Channel Layers
- Author
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Yu-Ching Tsao, Ting-Chang Chang, and Mao Chou Tai
- Subjects
Work (thermodynamics) ,Materials science ,Condensed matter physics ,02 engineering and technology ,Swing ,010402 general chemistry ,021001 nanoscience & nanotechnology ,01 natural sciences ,0104 chemical sciences ,Stress (mechanics) ,Thin-film transistor ,Thermal ,Degradation (geology) ,0210 nano-technology ,Layer (electronics) ,Communication channel - Abstract
In this work, an opposite sub-threshold swing trend of I-curve to C-V curve in tri-layer IGZO TFT is observed. Thermal and electrical field effects during stress duration is investigated to clarify this behavior. Results indicate a carrier distribution migration phenomenon; carriers are away from the gate insulator surface after self-heating stress which is caused by defect generations at channel/GI interface. Since carrier tends to locate at the middle layer (In-rich layer) after self-heating stress, carriers away from surface defects leads to a better subthreshold swing in I-V curve. However, C-V curves detects the information of defects leading to S.S degradation.
- Published
- 2019
24. Dynamic switching-induced back-carrier-injection in a-InGaZnO thin film transistors
- Author
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Mao-Chou Tai, Yu-Xuan Wang, Ting-Chang Chang, Yu-Lin Tsai, Hong-Yi Tu, Yu-Ching Tsao, Chih-Chih Lin, and Bo-Shen Huang
- Subjects
Dynamic switching ,Materials science ,Acoustics and Ultrasonics ,Thin-film transistor ,business.industry ,Optoelectronics ,Condensed Matter Physics ,business ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials - Abstract
In this work, degradation due to carrier injection at the etch-stop layer was observed under dynamic switching. A significant threshold voltage shift is observed in alternating current stress but is absent in direct current stress. A model which transitions from the accumulation to depletion phases indicates electron-trapping at the etch-stop layer since the transition time is insufficient for carriers to drift back to the source/drain electrodes. Results are discussed through both horizontal and lateral band diagrams to confirm back channel injections. Also, comparing transfer curves with capacitance-voltage curves at the same threshold voltage in different structure devices provides direct evidence of electron-trapping regions. Finally, COMSOL simulation is performed to confirm the difference in electron-trapping between back channel and corner regions, a difference which leads to an abnormal hump during capacitance-voltage measurements.
- Published
- 2020
25. Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors
- Author
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Yu-Lin Tsai, Hong-Yi Tu, Yu-Ching Tsao, Chih-Chih Lin, Shin-Ping Huang, Yu-Xuan Wang, Tsung-Ming Tsai, Yu-Zhe Zheng, Ting-Chang Chang, Hui-Chun Huang, Chia-Chuan Wu, Chuan-Wei Kuo, Mao-Chou Tai, and Ya-Ting Chien
- Subjects
010302 applied physics ,Materials science ,Acoustics and Ultrasonics ,Condensed matter physics ,Transistor ,Gate insulator ,Electron trapping ,02 engineering and technology ,Silicon thin film ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,01 natural sciences ,Bias stress ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,law.invention ,Stress (mechanics) ,Hysteresis ,law ,0103 physical sciences ,Degradation (geology) ,0210 nano-technology - Abstract
Degradation in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (S.S.) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in S.S. values which appears in hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.
- Published
- 2020
26. Flexible low-temperature polycrystalline silicon thin-film transistors
- Author
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Mao-Chou Tai, Yu-Ching Tsao, Wan-Ching Su, Shin Ping Huang, Ting-Chang Chang, Po-Hsun Chen, and Guan Fu Chen
- Subjects
Flexibility (engineering) ,Materials science ,Mechanical Engineering ,Transistor ,Low-temperature polycrystalline silicon ,engineering.material ,Commercialization ,Engineering physics ,Flexible electronics ,law.invention ,Reliability (semiconductor) ,Polycrystalline silicon ,law ,Thin-film transistor ,lcsh:TA401-492 ,engineering ,lcsh:Materials of engineering and construction. Mechanics of materials ,General Materials Science - Abstract
In today's society, displays are indispensable for digital interaction and personal contact. Therefore, the development of displays is an urgent need for the next generation. Leading the commercialization trends is the development of industrial, high-resolution, portable, and multifunctional displays. Moreover, for small-size portable displays, the most critical factor affecting future applications is their flexibility. Among the various materials that can act as the channel layer, low-temperature polycrystalline silicon (LTPS) is a potential candidate for next-generation portable displays, which require high resolution and stable reliability, and which can achieve virtual reality applications. This article is a review of the development of the LTPS thin-film transistors (TFTs) on soft and flexible electronics, especially the effect of mechanical strain. This article starts by providing an overview of the difficulties in fabricating LTPS TFTs on flexible substrates. The physical mechanism corresponding to each degradation caused by mechanical stress is presented next. Finally, to support the development of the flexible technologies and realize their commercialization, methods to overcome these mechanical strain-induced degradations are reported in three different aspects by understanding the physical degradation model. Keywords: Flexible LTPS TFT, Mechanical stress, Active layer design and mechanical absorption layer, Gate insulator quality improvement
- Published
- 2020
27. A Dual‐Gate InGaZnO 4 ‐Based Thin‐Film Transistor for High‐Sensitivity UV Detection
- Author
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Ying-Hsin Lu, Hua-Mao Chen, Hsiao-Cheng Chiang, Mao-Chou Tai, Yu-Ching Tsao, Yu-Lin Tsai, Po-Hsun Chen, Guan-Fu Chen, Hui-Chun Huang, Yu-Chieh Chien, Chih-Cheng Shih, Ting-Chang Chang, and Tsung-Ming Tsai
- Subjects
Materials science ,Mechanics of Materials ,business.industry ,Thin-film transistor ,Optoelectronics ,General Materials Science ,Uv detection ,business ,Dual gate ,Sensitivity (electronics) ,Industrial and Manufacturing Engineering ,Threshold voltage - Published
- 2019
28. Enhancing Repetitive Uniaxial Mechanical Bending Endurance at R=2mm Using an Organic Trench Structure in Foldable Low Temperature Poly-Si Thin-Film Transistors
- Author
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Yu-Ching Tsao, Wei-Han Chen, Shin-Ping Huang, Hong-Chih Chen, Shengdong Zhang, Ting-Chang Chang, Bo-Wei Chen, Jerzy Kanicki, Yu-Zhe Zheng, Po-Hsun Chen, Ann-Kuo Chu, Terry Tai-Jui Wang, and Min-Chen Chen
- Subjects
010302 applied physics ,Materials science ,Transistor ,Bend radius ,Bending ,engineering.material ,01 natural sciences ,law.invention ,Electronic, Optical and Magnetic Materials ,Stress (mechanics) ,Polycrystalline silicon ,law ,Thin-film transistor ,0103 physical sciences ,Trench ,engineering ,Degradation (geology) ,Composite material ,Electrical and Electronic Engineering - Abstract
At bending radius smaller than 2 mm, flexible low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) suffer from strong uniaxial mechanical stress and demonstrate severe degradation of electrical characteristics. Our previous study showed that repetitive mechanical uniaxial bending damages the gate insulator, causing carriers to trap into it. Here, degradation after channel width-axis direction bending was found to be more pronounced than after channel length-axis bending. In order to alleviate this degradation, an organic structure flexible LTPS TFT was proposed to enhance the mechanical stress endurance. After 100000 iterations of uniaxial mechanical bending at ${R} = 2$ mm, degradation nearly disappeared in devices with this organic trench structure.
- Published
- 2019
29. Floating top gate-induced output enhancement of a-InGaZnO thin film transistors under single gate operations
- Author
-
Shengdong Zhang, Ting-Chang Chang, Mao-Chou Tai, Hsiao-Cheng Chiang, Hsi-Ming Chang, Yu-Xuan Wang, Yu-Lin Tsai, Yu-Ching Tsao, Yu-Chieh Chien, Ming-Chen Chen, and Jian-Jie Chen
- Subjects
010302 applied physics ,Materials science ,Physics and Astronomy (miscellaneous) ,business.industry ,Gate insulator ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Structural geometry ,021001 nanoscience & nanotechnology ,01 natural sciences ,Gate control ,Stress (mechanics) ,Thin-film transistor ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Optoelectronics ,Positive bias ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,0210 nano-technology ,Drain current ,business ,Hardware_LOGICDESIGN ,Voltage - Abstract
This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.
- Published
- 2018
30. Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors
- Author
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Yu-Chieh Chien, Sung-Chun Lin, Kuan Fu Chen, Yu-Ching Tsao, Chung-I Yang, Hsiao-Cheng Chiang, Shengdong Zhang, Ting-Chang Chang, Po-Yung Liao, Yi-Chieh Yang, Kuan-Chang Chang, Yu-Ju Hung, Bo-Wei Chen, Tsung-Ming Tsai, and Cheng-Yen Yeh
- Subjects
010302 applied physics ,Materials science ,Physics and Astronomy (miscellaneous) ,Annealing (metallurgy) ,Analytical chemistry ,chemistry.chemical_element ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Copper ,Ion ,Amorphous solid ,Active layer ,chemistry ,Thin-film transistor ,Transmission electron microscopy ,0103 physical sciences ,0210 nano-technology ,Spectroscopy - Abstract
This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (Ion) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis.
- Published
- 2017
31. Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors.
- Author
-
Hsiao-Cheng Chiang, Ting-Chang Chang, Po-Yung Liao, Bo-Wei Chen, Yu-Ching Tsao, Tsung-Ming Tsai, Yu-Chieh Chien, Yi-Chieh Yang, Kuan-Fu Chen, Chung-I Yang, Yu-Ju Hung, Kuan-Chang Chang, Sheng-Dong Zhang, Sung-Chun Lin, and Cheng-Yen Yeh
- Subjects
AMORPHOUS alloys ,THIN film transistors ,ZINC oxide ,COPPER electrodes ,TRANSMISSION electron microscopy - Abstract
This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO
4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (Ion ) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis. [ABSTRACT FROM AUTHOR]- Published
- 2017
- Full Text
- View/download PDF
32. Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors.
- Author
-
Yu-Ching Tsao, Ting-Chang Chang, Hua-Mao Chen, Bo-Wei Chen, Hsiao-Cheng Chiang, Guan-Fu Chen, Yu-Chieh Chien, Ya-Hsiang Tai, Yu-Ju Hung, Shin-Ping Huang, Chung-Yi Yang, and Wu-Ching Chou
- Subjects
- *
CAPACITANCE measurement , *ELECTRIC potential measurement , *ULTRAVIOLET radiation , *THIN film transistors , *SIMULATION software - Abstract
This work demonstrates the generation of abnormal capacitance for amorphous indium-galliumzinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
33. Extended wide band gap amorphous aluminium-doped zinc oxide thin films grown at liquid nitrogen temperature
- Author
-
Chia-Chuan Wu, J. W. Chiou, Hsiung Chou, B J Chen, Shih-Jye Sun, T F Liao, M S Yang, and Yu-Ching Tsao
- Subjects
Materials science ,Acoustics and Ultrasonics ,Band gap ,Mineralogy ,Sputter deposition ,Condensed Matter Physics ,Nanocrystalline material ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,Amorphous solid ,Carbon film ,Amorphous carbon ,Chemical engineering ,Transmission electron microscopy ,Thin film - Abstract
Amorphous aluminium-doped zinc oxide (AZO) thin films are grown by standard RF sputtering at low temperatures on glass substrates. Due to poor thermal conductivity and thermal energy generated by the sputter gun, controlling the substrate surface temperature is the key to controlling the growth of amorphous and nanocrystalline films. The ratio of grains and amorphous part of the films can be controlled by selective growth conditions. During a transmission electron microscope (TEM) inspection process, the amorphous films react immediately and strongly with an electron beam and transform to a mixture of amorphous and nanocrystalline phases. The films having a mixture of amorphous and nanocrystalline phases, either as-grown or after transformation by irradiation of the electron beam, are stable in the TEM inspection, indicating that the low interface energy stabilizes the mixture phase. The optical band gap increases with the content of amorphous phase and is 4.3eV for pure amorphous AZO films. (Some figures in this article are in colour only in the electronic version)
- Published
- 2011
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