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As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

As electronic product becomes smaller and lighter with an increasing number of function ↚ the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of TSV interposers and TGV interposers with fine pitch high aspect ratio through vias.

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from −40 cereuses deg to 80 cereuses deg.

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50µm diameter) are fabricated today with 300µm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000cycle from −40 cereuses deg to 80 cereuses deg.

As electronic products becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of silicon and glass interposers with fine pitch metalized through via. High frequency transmission characteristics were measured with TSV and TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from −40 Celsius deg to 80 Celsius deg.

In this study, observation and simulation data are analyzed to examine the causes of the rapid rise of surface air temperature in the inland area of northwestern Kanto Plain, Central Japan on 20 February 2009. A numerical simulation using the Weather Research and Forecasting (WRF) model shows that the temperature rise was mainly brought about by a downward wind with adiabatic heating over the area. Backward trajectory analysis indicates that the descending air parcel came from the southward warm area, in relation to the passage of a cyclone over the Kanto Plain. At about 1600 JST, the wind at the 850 hPa surface was divided into northward and southward by the central-Japan mountains, and converged over the northwestern Kanto area, which implied the formation of a downward wind. We suggest that the downward wind had the feature of a dry foehn, which was not accompanied by a precipitation process.

本研究では東京都区部において2004年春のソメイヨシノの開花日を調査し,気温分布との関係を考察した.その結果,開花日の分布は2004年3月の平均気温の分布とよい対応を示しており,都心部の高温域で開花が早く,郊外部の低温域で遅い傾向がみられた.よって，ヒ-トアイランド現象が開花日に影響を与えていることが明らかとなった。また,開花日と3月の平均気温との関係は,温度変換日数(積算気温のモデル)を用いて,開花日に至るプロセスを評価することによって裏付けられた.各観測地点における開花日から2004年3月の平均気温を推定し,その精度を実測値との比較により評価した.その結果,推定値と実測値との誤差はほとんどの地点で±0.3°C以内で,二乗平均平方根誤差(RMSE)は0.2°Cであった.よって開花日がヒ-トアイランドなどロ-カルスケ-ルの気候環境を表す指標となり得ると考えられる.

Recent changes in plant phenology such as budding, flowering, and change in color and falling of leaves are related to global warming and heat islands developing in city areas. Some studies have evaluated how secular urban climates influence the flowering dates of cherry blossoms (Prunus yedoensis). However, few studies have observed both the spatial urban climate and the flowering dates of P. yedoensis at the same time in a city. In this study, the authors researched the relationship between the spatial urban climate and the flowering dates of P. yedoensis in Kumagaya City, Saitama Prefecture, Japan. It was clear that the flowering dates of P. yedoensis corresponded to urban temperatures. It is concluded that heat island effects influence the flowering dates of P. yedoensis, and therefore those flowering dates are possible indicators of climatic change and urban warming. Moreover, it is possible to evaluate the effects of urban warming by applying the spatial variation in Kumagaya City to the year-to-year variation in flowering dates of P. yedoensis at the Kumagaya Meteorological Observatory. The authors analyzed the urban climate in Kumagaya City, including a comparison with urban climate data from 1956. The horizontal and temporal changes of heat islands were closely related to degree of urbanization in the urban area and the physical nature of surface coverage (values of 1/cρ√κ)

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;! however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several months. Fully populated wafers with > 100,000 through holes (50μm diameter) are fabricated today with 300pm thick glass. This paper presents the demonstration of glass interposers with fine pitch through glass vias(TGV), ! with 6um RDL lithography. TGVs of 50μm in diameter and 200μm in pitch were formed successfully on 300μm thick alkali-free glass by Focused Electrical Discharging Method (FEDM). The TGVs were filled with solid Copper (Cu) using a void-free electroplating of optimized periodic pulse reverse(PPR) process and chemical mechanical polishing (CMP) as well as the TSVs. Highly insulating TGV with double side polymer insulation resulted in TGV with an insertion loss of less than 0.23dB at 20GHz. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TGV at 200μm pitch passed 1000 thermal cycles from -40Cdeg to 85Cdeg.

Advanced vertical interconnect technology that combines traditional HDI (high density interconnect) structures feature micro-vias and conductive paste-vias was developed to fabricate multilayer printed circuit board, such as ultra-multilayer printed circuit board like probe card or IC testing board, having excellent electrical performance, mechanical reliability and mass productivity at reasonable cost. This advanced multilayer printed circuit board constituted of high elastic modulus thermosetting dielectric composition with interstitial via holes (IVH) and/or Cu micro-vias (HDI), besides sintered conductive paste-vias buried in low elastic modulus thermosetting dielectric composition. The latter composition will properly act as mechanical buffering layer of vertical interconnection between upper and lower multilayer boards. This paper discuss about manufacturing process factor, that is pre-curing temperature, affecting the optimum electrical performance at the interface of HDI Cu lands and conductive paste with interposing low elastic modulus dielectric material in the first place. In the second place, analysis of observations for the micro structure and sintering condition at the interface of conductive paste and HDI Cu land by using SEM and energy dispersive X-ray spectrometry (EDX). In addition, mechanical reliabilities, estimated by using structural analysis method and signal transmission properties by way of this buried conductive paste using frequency and time-domain simulation analyses were discussed.. From these results, this advanced vertical interconnect technology with sintered conductive paste and low elastic dielectric has sufficient mechanical reliability and electrical property for passing high-speed signal up to 15 Gbps.

We have developed B2itTM (Buried Bump interconnection technology) printed wiring boards (PWB's) for high density and high performance wiring boards or substrates. Ordinary PWB's have low thermal conductivity because of their organic materials, compared with ceramic substrates and so on. The B2itTM PWB's have filled via holes by silver paste bumps to connect wiring lines between neighbor layers. The feature is different from ordinary PWB's having copper-plated through holes. This paper reports the thermal management properties for the B2itTM PWB's by measuring the thermal resistance of several filled via hole situation. And a thermal conductivity of the via hole material was simulated from the measurement values. As the results, the thermal conductivity of the via hole was very high to compare with that of the normal printed silver paste, and the B2itTM PWB's had good thermal management property enough to high density packaging.

The simplest expression of the urban surface is alternation of buildings and streets. The space above a street between buildings is called an urban canyon. Air circulation in an urban canyon, which affects the behavior of air pollutants emitted by motor vehicles, is a significant factor in investigating the urban environment. However, because of the difficulty in installing observation equipment, few observational studies on air circulation have been conducted in actual urban canyons. In the present study, in order to detect three-dimensional air circulation in an urban canyon quantitatively, three wind vector components were measured using interval camera and tracer balloons with a known ascending rate. The three-dimensional position of the tracer balloons was determined by microscopic measurements of the position and diameter of the balloons on the negatives taken at an interval of two seconds (Fig. 2, Photo 1). Thereafter, wind vectors that drive the tracer balloons were calculated by subtracting the ascending rate of the respective balloons from the vectors of balloon movement. The direction and length of the target canyon, located on the former campus of Hiroshima University in Hiroshima City, are NNW-SSE and about 80 m, with canyon height and width of about 18 m and 25 m, respectively (Fig. 1). During the observation periods, wind at 3 m above the rooftop level blew obliquely to the canyon direction, and wind velocity ranged from 1.6 to 2.3 m/s (Table 2). The results of observations can be summarized as follows: 1) Measurement of air circulation using tracer balloons and interval camera is a simple method for the set-up of observation equipment, and can be used without serious error (Table 1). Therefore, this method is applicable to actual urban canyons. 2) Although there were marked contrasts in the distribution of air and surface temperatures in a canyon, no significant difference was observed in air circulation between approximately noon and during the afternoon (Fig. 4). Therefore, the air circulation detected in this study could be induced mechanically by downward air motion due to the blocking effect of leeward buildings. Air flow parallel to the canyon direction was in a spiral stream (Fig. 3). Moreover, the intensity of circulation defined as wind vorticity (Fig. 5) in the cross-section of the canyon correlated positively and significantly with the wind component perpendicular to the canyon direction at 3 m above the rooftop level (Fig. 6). 3) Wind velocity parallel to the canyon direction increased toward the leeward canyon direction (Fig. 3 (b), (c)). The increase in the wind component rate parallel to the canyon direction was nealy proportional to the downward wind velocity at the canyon top (Fig. 7), i. e., the net downward air flow from the canyon top should accelerate wind velocity in the canyon along the canyon direction. In conclusion, it was observationally confirmed that air circulation in the urban canyon spirals with descending and ascending motions on the leeward and windward sides of the canyon versus to the wind aloft, respectively. Moreover, the intensity of air circulation varies according to the wind velocity aloft, and wind velocity parallel to the canyon direction is accelerated by net inflow from the canyon top. Since the wind conditions in the present observation were rather limited, further observations are needed for various wind velocities and directions.

This paper describes one of the new package cooling concepts using a phase-changing-material (PCM), to be applied for the development of high-density packaging. A low-cost alloy, composed of Bi/Pb/Sn/In, the melting points of each of the elements of which are less than 70°C, was used as the PCM. Experiments were conducted using this alloy and thermal network method was applied for the analysis of phase-changing phenomena. It was confirmed that the surface temperature of the opposite side of the substrate could be fixed at the PCM's melting temperature for several minutes by thermal absorption effect while the PCM phase changed from its original solid state into the liquid state. It has also been confirmed, in the present work, that thermal network method could be used as a personal computer base engineering tool for the thermal design of a package with a PCM.

Informations on the cold weather and climatic disasters during part of the Little Ice Age for 17th to 18th Century in Japan were obtained from tree ring widths and some kinds of historical documents.Tree rings were analyzed both at Northeastern Japan (Fukushima Pref.) and Southwestern Japan (Okayama Pref.) mostly in Shinto Shrines' precincts. The daily weather records described in old personal documents such as diaries were inquired into at Hirosaki City (Aomori Pref.) for Fukushima's tree rings and at Tsuyama City (Okayama Pref.) for Okayama's tree rings. In this study, the snowy days' rate is used as an indicator of winter coldness. It is defined as the percentage of the number of days with snowfall to that with precipitation, that is, the total of rainy and snowy days.As a result, it could be concluded that the tree ring widths are narrower in the year of larger snowy days' rate. In Southwestern Japan, it is also considered that the drought summer as well as coldest winter caused the worse growth of trees.

To hermetically seal a hybrid IC with several EPROM IC ships, sapphire windows are brazed to a metal cap. Since it was necessary to investigate the pressure resistance of the sapphire windows, stress analysis was performed using the finite element method. In stress analysis, we consider the thermal stress generated in brazing the sapphire window on the metal cap, the forced stress generated in the hermetic seal process of the hybrid IC and the pressured stress generated in the hybrid IC. The allowable stress in sapphire was measured by the bending test with two-point support to obtain the stress limit of sapphire. The theoretical and experimental results were compared to confirm the validity of the analytical model. The analytical method developed in this study will be helpful to achieve high reliability in a hybrid IC with sapphire windows.

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. In other aspect, IT (information technology) products supported on broadband network communication technologies. It changes from the cable communication by the digital circuit to the wire less communication by analogue and mixed-signal technologies. We have researched requirements for the design of next generation system in packaging module from the several points of view which include line width, pad pitch, clock, frequency, interconnection delay and number of passive components. Based on this, we presented a new concept packaging module model. The new module, silicon through integration platform, has through interconnection via, fine wiring build up layers, and embedded passives. This paper reports the result, which focus on the various electrical characteristics of silicon through substrate, and electrical simulation design technology for system in package. We have tried very accurate impedance matching design using 2D electromagnetic simulation and TDR (Time Domain Refrectometry) measurement technology. To investigate high frequency characteristic of hi-speed transmission line and silicon through interconnection, we have tried 3D electromagnetic simulation and VNA (vector network analyser) measurement. Thus, we have obtained good performance of high frequency transmission line and optimal design rule for system in package.

Urban-biometeorology, i.e., biometeorological study on the urban climate is regarded as both old and/or new science. Studies on two topics are reviewed: the thermal or chemical impact of urban climate on human health, and the relation between urban climate and vegetation.

This paper describes one of the new package cooling technology concepts using a phase changing material (PCM) which would help develop high density packaging. A low cost alloy, composed of Bi/Pb/Sn/In whose melting point is 57°C, was used as the PCM. Thermal experiments using the abovementioned alloy had been studied by the authors.1) It was confirmed that the substrate back surface temperature could be fixed at the PCM's melting temperature for several minutes by thermal absorption, while the PCM phase changed from its original solid state into the liquid state. Also, in the present work, it has been confirmed that thermal network method is practically useful using a personal computer for the thermal design of a package with a PCM.

This paper describes a simulation model used to predict the transient temperature rise in multichip packages. The model was designed to consider not only heat conduction but also thermal radiation and natural convection as well as simplicity. The calculations were made with the designed model (MODEL 1), in addition to only a heat conduction model (MODEL 2). The experiments were performed for a ceramic substrate, which had capacitor chips. It had a 36 cm2 surface area -32 watts heat flow rate. The calculation results with MODEL are in good agreement with the experimental data. However, the results with MODEL 2 are 10 percent higher than those with MODEL 1. It was found that MODEL 1 is very useful for high density multichip package thermal design.

This is the last in a series of reports on various aspects of geographic research in Japan. The series has been sponsored by the United States Committee for the International Geographic Union in anticipation of the 1980 IGC in Tokyo. Like its predecessors, this report has been modified by H. Jesse Walker, member of the Committe, for the benefit of English-speaking readers of THE PROFESSIONAL GEOGRAPHER.

This paper describes a simulation model used to predict the transient temperature rise for multichip packages. The model was designed to consider not only heat conduction but also thermal radiation and natural convection, as well as simplicity. The calculations were made with the designed model (MODEL 1), in addition to only a heat conduction model (MODEL 2). The experiments were performed for a ceramic substrate, which has 4 high power transister chips and other chips, such as IC, resistor and capacitor chips. It has a 36 cm2 surface area-32 watts heat flow rate. The calculation results with MODEL 1 are in good agreement with the experimental data. However, the results with MODEL 2 are 10 percent higher than those with MODEL 1. It was found that MODEL 1 is very useful for high density multi-chip package thermal design.