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Accurate control of doping and fabrication of metal contacts on n-type germanium nanowires (GeNWs) with low resistance and linear characteristics remain a major challenge in germanium-based nanoelectronics. Here, we present a combined approach to fabricate Ohmic contacts on n-type-doped GeNWs. Phosphorus (P) implantation followed by millisecond rear-side flash lamp annealing was used to produce highly n-type-doped Ge with an electron concentration in the order of 10^19-10^20 cm^{-3}. Electron beam lithography, inductively coupled plasma reactive ion etching, and nickel (Ni) deposition were used to fabricate GeNW-based devices with symmetric Hall bar configuration, which allows detailed electrical characterization of the NWs. Afterward, rear-side flash lamp annealing was applied to form Ni germanide at the Ni-GeNWs contacts to reduce the Schottky barrier height. The two-probe current-voltage measurements on P-doped GeNWs exhibit linear Ohmic behavior. Also, the size-dependent electrical measurements showed that carrier scattering near the NW surfaces and reduction of the effective NW cross-section dominate the charge transport in the GeNWs.

Silicon junctionless nanowire transistors (JNTs) have shown excellent sensitivity to record-low concentrations of the protein streptavidin in liquid phase. However, JNTs have not yet been tested for sensing in gas phase. Here we present the fabrication and initial electrical characterisation of JNT-based electronic sensors for detection of atmospheric free radicals such as hydroxyl (•OH) and nitrate (•NO3), which are the main drivers of chemical processes in the atmosphere. The aim of this work is to develop small, lowcost JNT-based nanosensors for radical detection. Silicon-on-insulator wafers were doped by ion implantation and flash-lamp annealing. Device patterning was based on electron beam lithography, inductively-coupled reactive ion etching, metal deposition and lift-off. Initial electrical characterisation and gas sensing experiments on fabricated devices proved their good performance and potential suitability for detection of atmospheric free radicals. Additional Information: Sayantan Ghosh delivered this presentation for Deutschen Physikalische Gesellschaft e.V. (DPG) conference 2022. RADICAL represents a 'Fundamental Breakthrough in Detection of Atmospheric Free Radicals'. Find out more on the RADICAL project website: radical-air.eu The RADICAL project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement number 899282. &nbsp

Air quality and climate change are among the biggest societal challenges that we face today. Atmospheric free radicals, particularly hydroxyl (•OH) and nitrate (•NO3), are the drivers of chemical processes that determine atmospheric composition and thus influence local and global air quality and climate. Detecting and understanding the behavior of radical species in the atmosphere is therefore of paramount importance and hence a major research goal in atmospheric science. Current techniques for measuring radicals are based on spectroscopic and mass spectrometric methods, which although sensitive and robust, are technically complex, cumbersome, and expensive. The central aim of this project is to develop organic surfaces on confined 1D interfaces to fabricate radical sensors on a Silicon junctionless nanowire transistor (Si JNT) platform. Silicon junctionless nanowire transistors (JNTs) have recently detected record low concentrations (down to the zeptomolar range) of the protein streptavidin in liquid phase. However, JNTs have not yet been tested for sensing in gas phase. Additional Information: Sayantan Ghosh delivered this presentation for RSC Twitter Conference. RADICAL represents a 'Fundamental Breakthrough in Detection of Atmospheric Free Radicals'. Find out more on the RADICAL project website: radical-air.eu The RADICAL project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement number 899282.

Among other new device concepts, nickel silicide (NiSix)-based Schottky barrier nanowire transistors are projected to supplement down-scaling of the complementary metal-oxide-semiconductor (CMOS) technology as its physical limits are reached. Control over the NiSix phase and its intrusions into the nanowire are essential for superior performance and down-scaling of these devices. Several works have shown control over the phase, but control over the intrusion lengths has remained a challenge. To overcome this, we report a novel millisecond-range flash-lamp-annealing (FLA)-based silicidation process. Nanowires are fabricated on silicon-on-insulator substrates using a top-down approach. Subsequently, Ni silicidation experiments are carried out using FLA. It is demonstrated that this silicidation process gives unprecedented control over the silicide intrusions. Scanning electron microscopy and high-resolution transmission electron microscopy are performed for structural characterization of the silicide. FLA temperatures are estimated with the help of simulations.

Here, we report the observation of negative photoconductance (NPC) effect in highly arsenic-doped germanium nanowires (Ge NWs) for the infrared light. NPC was studied by light-assisted Kelvin probe force microscopy, which shows the depletion of carriers in n-Ge NWs in the presence of infrared light. The trapping of photocarriers leads to high recombination of carriers in the presence of light, which is dominant in the n-type devices. Furthermore, a carrier trapping model was used to investigate the trapping and detrapping phenomena and it was observed that the NPC in n-Ge occurred, because of the fast trapping of mobile charge carriers by interfacial states. The performance of n-type devices was compared with p-type NW detectors, which shows the conventional positive photoconductive behavior with high gain of 104. The observed results can be used to study the application of Ge NWs for various optoelectronic applications involving light tunable memory device applications.

The fabrication of p-type silicon junctionless tri-gate transistors and their temperature dependent transport studies are reported in this work. The fabricated transistors have shown a good transfer characteristic down to a low temperature of ~ 80 K with an ON/OFF ratio of 106. The threshold voltage and the subthreshold slope were found to be dependent on temperature. In particular, the threshold voltage and the flat band voltage have positive slopes of 2.24 and 1.19 mV K−1, respectively, with temperature. Channel resistance was found to be increasing with decreasing temperature. The devices have shown a typical 1/f noise behavior in the frequency range of (1–50) Hz and 1/f2 type behavior in the frequency range of (50–100 Hz). At a temperature of 4.2 K, current vs. gate voltage characteristic at a fixed source drain bias shows clear coulomb peaks with different intervals for different gate bias voltages and the observed spikes were consistent within the sub-bands. We relate this to the single hole tunneling, mediated by the charged acceptors available in the channel region. Coupling strength of the dopants was also studied.

Introduction: For decades the miniaturization of logic circuitry was a result of down scaling of the field effect transistor (FET). This scaling has reached its end and, therefore, new device materials and concepts have been under research for the last years. One approach is to increase the functionality of an individual device rather than scaling down its size. Such a device concept is the reconfigurable FET (RFET), which can be configured to n- or p-polarity dynamically [1]. RFETs are based on Schottky barrier FETs and feature an intrinsic Si nanowire (NW) channel. The Schottky junctions are formed by placing Nickel (Ni) contacts on both ends of the NW and conductive Ni-silicide segments are formed in the NW by an annealing process. In RFETs, two gates are usually placed on top of these Schottky junctions and by the application of electrostatic potential at the gates unipolar n- or p-transport is tuned in the channel. There are several Ni-silicide phases out of which NiSi2 is preferred as it yields sharp NiSi2-Si junctions. Moreover, its metal work function is near the mid bandgap of Si. This enables tuning the RFET to n- or p-transport by respectively bending the bands when applying electrostatic potential at the gates (Fig. 1). Top-down fabrication of Schottky barrier FETs is a pre-requisite for the large-scale integration of RFETs. The challenges in this fabrication process include proper patterning of NWs, obtaining symmetric p- and n-currents and the scalability of the devices. The first two tasks have been solved as reported in [2]. However, the lack of controllable intrusion of silicide into the NWs remains an obstacle for device scalability [3-5]. Here we report that a silicidation process based on millisecond flash lamp annealing (FLA) significantly improves the uniformity of silicide intrusion at the two ends of the NWs. Such a gain in silicidation control will decisively allow creating RFETs with short channel lengths. Fabrication: The devices are fabricated on silicon-on-insulator (SOI) substrates with 20 nm undoped top Si layer and 102 nm buried oxide. Electron beam lithography (EBL) and dry etching are used to fabricate NWs with 20 nm width as described in [3]. NWs are oxidized with a rapid thermal process and a ~6 nm thick SiO2 shell is formed to passivate NW surface. After wet etching SiO2 from desired areas, Ni contacts are placed in those areas using EBL and Ni evaporation. FLA is used for silicidation of the NWs and the results show equally long silicide intrusions (Fig. 2). Results: The FLA process time is much shorter (0.5-20 ms) compared to conventional rapid thermal annealing (RTA) [6]. FLA based silicidation process is developed which, unlike previously reported RTA based processes, can deliver scalable RFETs. High resolution TEM (HRTEM) shows the formation of the desired NiSi2 phase and atomically abrupt Schottky junctions (Fig. 4). This is also confirmed by element mapping based on energy dispersive X-ray spectroscopy (EDXS) (Fig. 3). The transfer characteristics of the device with back-gate operation show an ambipolar behavior with an ON/OFF ratio of 9 orders of magnitude (Fig. 5). The gate voltage (VBG) was swept from -30 V to 30 V and the drain to source voltage (VD) was varied from 0.25 V to 0.75 V. The unipolar behavior can be tuned by fabricating two or more top gates. This will also reduce the additional hysteresis caused by using the buried oxide as a very thick gate dielectric. Applications: The FLA-based silicidation process enables channel scaling. Devices based on this process show promising results and have potential applications as devices with reduced power consumption and low chip area [7]. These RFETs can also be used for the fabrication of power-efficient multi-independent gate-based logic circuits [8]. Moreover, the number of transistors and the chip area consumption can be reduced with the help of these transistors, preserving at the same time the functionality of the integrated circuits [9]. 1.Heinzig, A. et al., Nano Lett., 2011.12(1):pp.119-124. 2.Simon, M. et al.,IEEE Trans Nanotechnol, 2017.16(5):pp.812-819. 3.Khan, B.M. et al., Appl. Sci. 2019. 9(17),3462. 4.Habicht, S. et al., Nanotechnology, 2010. 21(10): pp.105701. 5.Ogata, K. et al., Nanotechnology,2011.22(36):pp.365305. 6.Rebohle, L. et al., Semicond Sci Technol, 2016. 31(10): pp.103001. 7.Gaillardon, P.E. at al., in LATS, 2016, pp.195-200. 8.Rai, S. et al., IEEE Transactions VLSI, 2019.27(3):pp.560-572. 9.Raitza, M., et al., in DATE.2017,pp.338-343.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

A laboratory measurement of the α -decay half-life of 190 Pt has been performed using a low background Frisch grid ionisation chamber. A total amount of 216.60(17) mg of natural platinum has been measured for 75.9 days. The resulting half-life is ( 4.97 ± 0.16 ) × 10 11 years , with a total uncertainty of 3.2%. This number is in good agreement with the half-life obtained using the geological comparison method.

This article presents a review of various methods for extracting the key parameters of junctionless (JL) MOSFETs, namely, the threshold voltage, flat-band voltage, doping concentration, carrier mobility, and parasitic series resistance. The applicability and limitations of different methods are analyzed using numerical simulations and experimental data for planar and tri-gate nanowire JL transistors with various nanowire widths.

The transport properties of novel device architectures depend strongly on the morphology and the quality of the interface between contact and channel materials. In silicon nanowires with nickel silicide contacts, NiSi 2–Si interfaces are particularly important as NiSi 2 is often found as the phase adjacent to the silicide–silicon interface during and after the silicidation. The interface orientation of these NiSi 2–Si interfaces as well as the ability to create abrupt and flat interfaces, ultimately with atomic sharpness, is essential for the properties of diverse emerging device concepts. We present a combined experimental and theoretical study on NiSi 2–Si interfaces. Interfaces in silicon nanowires were fabricated using silicidation and characterized by high-resolution (scanning) transmission electron microscopy. It is found that {111} interfaces occur in ⟨110⟩ nanowires. A tilted interface and an arrow-shaped interface are observed, which depends on the nanowire diameter. We have further modeled NiSi 2–Si interfaces by density functional theory. Different crystallographic orientations and interface variations, e.g., due to interface reconstruction, are compared with respect to interface energy densities. The {111} interface is energetically most favorable, which explains the experimental observations. Possible ways to control the interface type are discussed.

Films of self assembled diblock copolymers (BCPs) have attracted significant attention for generating semiconductor nanoarrays of sizes below 100 nm through a simple low cost approach for device fabrication. A challenging abstract is controlling microdomain orientation and ordering dictated by complex interplay of surface energies, polymer–solvent interactions and domain spacing. In context, microphase separated poly (styrene-b-ethylene oxide) (PS-b-PEO) thin films is illustrated to fabricate nanopatterns on silicon and germanium materials trenches. The trenched templates was produced by simple electron beam lithography using hydrogen silsesquioxane (HSQ) resist. The orientation of PEO, minority cylinder forming block, was controlled by controlling trench width and varying solvent annealing parameters viz. temperature, time etc. A noticeable difference in microdomain orientation was observed for Si and Ge trenches processed under same conditions. The Ge trenches promoted horizontal orientations compared to Si due to difference in surface properties without any prior surface treatments. This methodology allows to create Ge nanopatterns for device fabrication since native oxides on Ge often induce patterning challenges. Subsequently, a selective metal inclusion method was used to form hardmask nanoarrays to pattern transfer into those substrates through dry etching. The hardmask allows to create good fidelity, low line edge roughness (LER) materials nanopatterns.

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10(20) atoms cm(-3). Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.

The directed self-assembly of block copolymer (BCP) materials in topographically patterned substrates (i.e., graphoepitaxy) is a potential methodology for the continued scaling of nanoelectronic device technologies. In this Communication, an unusual feature size variation in BCP nanodomains under confi nement with graphoepitaxially aligned cylinder-forming poly(styrene)- block -poly(4-vinylpyridine) (PS- b -P4VP) BCP is reported. Graphoepitaxy of PS- b -P4VP BCP line patterns (C II ) is accomplished via topography in hydrogen silsequioxane (HSQ) modifi ed substrates and solvent vapor annealing (SVA). Interestingly, reduced domain sizes in features close to the HSQ guiding features are observed. The feature size reduction is evident after inclusion of alumina into the P4VP domains followed by pattern transfer to the silicon substrate. It is suggested that this nanodomain size perturbation is due to solvent swelling effects during SVA. It is proposed that using a commensurability value close to the solvent vapor annealed periodicity will alleviate this issue leading to uniform nanofi ns.

'Directing' block copolymer (BCP) patterns is a possible option for future semiconductor device patterning, but pattern transfer of BCP masks is somewhat hindered by the inherently low etch contrast between blocks. Here, we demonstrate a 'fab' friendly methodology for forming well-registered and aligned silicon (Si) nanofins following pattern transfer of robust metal oxide nanowire masks through the directed self-assembly (DSA) of BCPs. A cylindrical forming poly(styrene)-block-poly(4-vinyl-pyridine) (PS-b-P4VP) BCP was employed producing 'fingerprint' line patterns over macroscopic areas following solvent vapor annealing treatment. The directed assembly of PS-b-P4VP line patterns was enabled by electron-beam lithographically defined hydrogen silsequioxane (HSQ) gratings. We developed metal oxide nanowire features using PS-b-P4VP structures which facilitated high quality pattern transfer to the underlying Si substrate. This work highlights the precision at which long range ordered [similar]10 nm Si nanofin features with 32 nm pitch can be defined using a cylindrical BCP system for nanolithography application. The results show promise for future nanocircuitry fabrication to access sub-16 nm critical dimensions using cylindrical systems as surface interfaces are easier to tailor than lamellar systems. Additionally, the work helps to demonstrate the extension of these methods to a 'high [small chi]' BCP beyond the size limitations of the more well-studied PS-b-poly(methyl methylacrylate) (PS-b-PMMA) system.

The semiconductor industry has already entered the sub-10 nm region, which has led to the development of cutting-edge fabrication tools. However, there are other factors that hinder the best outcome of these tools, such as the substrate and resist materials, pre- and postfabrication processes, etc. Among the lithography techniques, electron beam lithography (EBL) is the prime choice when a job requires dimensions lower than 10–20 nm, since it can easily achieve such critical dimensions in reasonable time and effort. When obtaining pattern features in single nanometer regime, the resist material properties play an important role in determining the size. With this agenda in mind, many resists have been developed over the years suitable for attaining required resolution in lesser EBL writing time. This review article addresses the recent advancements made in EBL resists technology. It first describes the different lithography processes briefly and then progresses on to the parameters affecting the EBL fabrications processes. EBL resists are then bifurcated into their “family types” depending on their chemical composition. Each family describes one or two examples of the new resists, and their chemical formulation, contrast-sensitivity values, and highest resolution are described. The review finally gives an account of various alternate next-generation lithography techniques, promising dimensions in the nanometer range.

The complex physics of the interaction between short-pulse ultrahigh-intensity lasers and solids is so far difficult to access experimentally, and the development of compact laser-based next-generation secondary radiation sources, e.g., for tumor therapy, laboratory astrophysics, and fusion, is hindered by the lack of diagnostic capabilities to probe the complex electron dynamics and competing instabilities. At present, the fundamental plasma dynamics that occur at the nanometer and femtosecond scales during the laser-solid interaction can only be elucidated by simulations. Here we show experimentally that small-angle x-ray scattering of femtosecond x-ray free-electron laser pulses facilitates new capabilities for direct in situ characterization of intense short-pulse laser-plasma interactions at solid density that allows simultaneous nanometer spatial and femtosecond temporal resolution, directly verifying numerical simulations of the electron density dynamics during the short-pulse high-intensity laser irradiation of a solid density target. For laser-driven grating targets, we measure the solid density plasma expansion and observe the generation of a transient grating structure in front of the preinscribed grating, due to plasma expansion. The density maxima are interleaved, forming a double frequency grating in x-ray free-electron laser projection for a short time, which is a hitherto unknown effect. We expect that our results will pave the way for novel time-resolved studies, guiding the development of future laser-driven particle and photon sources from solid targets.

To maintain semiconductor device scaling, in recent years industry has been forced to move from planar to non-planar device architectures. This alone has created the need to develop a radically new, non-destructive method for doping. Doping alters the electrical properties of a semiconductor, related to the access resistance. Low access resistance is necessary for high performance technology and reduced power consumption. In this work the authors reduced access resistance in top–down patterned Ge nanowires and Ge substrates by a non-destructive dopant in-diffusion process. Furthermore, an innovative electrical characterisation methodology is developed for nanowire and fin-based test structures to extract important parameters that are related to access resistance such as nanowire resistivity, sheet resistance, and active doping levels. Phosphine or arsine was flowed in a Metalorganic Vapour Phase Epitaxy reactor over heated Ge samples in the range of 650–700 °C. Dopants were incorporated and activated in this single step. No Ge growth accompanied this process. Active doping levels were determined by electrochemical capacitance–voltage free carrier profiling to be in the range of 1019 cm−3. The nanowires were patterned in an array of widths from 20–1000 nm. Cross-sectional Transmission Electron Microscopy of the doped nanowires showed minimal crystal damage. Electrical characterisation of the Ge nanowires was performed to contrast doping activation in thin-body structures with that in bulk substrates. Despite the high As dose incorporation on unpatterned samples, the nanowire analysis determined that the P-based process was the better choice for scaled features.

Display Omitted Study of a new electron beam resist, SML.Contrast is as high as PMMA.Dense grating with linewidth from ~5 to 8nm demonstrated in SML and ZEP.Etch resistance equivalent to ZEP resist. We present study on a novel, positive-tone electron beam lithography (EBL) resist known as SLM and compare its lithographic performance to well-established positive resists such as 950K polymethyl methacrylate (PMMA) and ZEP 520A. SML has been fabricated to have processing parameters similar to PMMA, but with enhanced functionality. Processing parameters such as film deposition, baking temperatures as well as the developers used for PMMA work well with SML resist.Contrast curve measurements were generated for different thicknesses of SLM and exposure voltages. Two temperature variants were employed for developing the resist with 7:3 IPA:water co-solvent developer, viz. room temperature and 0?C. To verify the resolution of SML resist, dense gratings of single pixel lines were compared to those fabricated using 950K PMMA and ZEP 520A resists. Fundamental pattern transfer skills of metal lift-off and dry etching were compared with ZEP. Metal lift-off was carried out using 5-10nm thick chromium metal and Microposit 1165 resist remover. The resilience of the SML resist to dry etching (ICP etching system with SF6 and C4F8 gas mixture) was compared to ZEP and PMMA resists and then dense gratings on ZEP and SML were etched into Si.The data obtained from the contrast curves show high contrast of the new resist. From the grating results, SML demonstrates very high resolution like ZEP and PMMA. The pattern transfer abilities of SML are also similar and in some aspects even outdo that of ZEP resist.

From Springer description: "We present the design considerations of an autonomous wireless sensor and discuss the fabrication and testing of the various components including the energy harvester, the active sensing devices and the power management and sensor interface circuits. A common materials platform, namely, nanowires, enables us to fabricate state-of-the-art components at reduced volume and show chemical sensing within the available energy budget. We demonstrate a photovoltaic mini-module made of silicon nanowire solar cells, each of 0.5 mm2 area, which delivers a power of 260 μW and an open circuit voltage of 2 V at one sun illumination. Using nanowire platforms two sensing applications are presented. Combining functionalised suspended Si nanowires with a novel microfluidic fluid delivery system, fully integrated microfluidic–sensor devices are examined as sensors for streptavidin and pH, whereas, using a microchip modified with Pd nanowires provides a power efficient and fast early hydrogen gas detection method. Finally, an ultra-low power, efficient solar energy harvesting and sensing microsystem augmented with a 6 mAh rechargeable battery allows for less than 20 μW power consumption and 425 h sensor operation even without energy harvesting."

Ge-on-Si and Ge-on-insulator (GeOI) are the most promising materials for the next-generation nanoelectronics that can be fully integrated with silicon technology. To this day, the fabrication of Ge-based transistors with a n-type channel doping above 5 × 1019 cm−3 remains challenging. Here, we report on n-type doping of Ge beyond the equilibrium solubility limit (ne ≈ 6 × 1020 cm−3) together with a nanoscale technique to inspect the dopant distribution in n++-p junctions in GeOI. The n++ layer in Ge is realized by P+ ion implantation followed by millisecond-flashlamp annealing. The electron concentration is found to be three times higher than the equilibrium solid solubility limit of P in Ge determined at 800 °C. The millisecond-flashlamp annealing process is used for the electrical activation of the implanted P dopant and to fully suppress its diffusion. The study of the P activation and distribution in implanted GeOI relies on the combination of Raman spectroscopy, conductive atomic force microscopy, and secondary ion mass spectrometry. The linear dependence between the Fano asymmetry parameter q and the active carrier concentration makes Raman spectroscopy a powerful tool to study the electrical properties of semiconductors. We also demonstrate the high electrical activation efficiency together with the formation of ohmic contacts through Ni germanidation via a single-step flashlamp annealing process.Ge-on-Si and Ge-on-insulator (GeOI) are the most promising materials for the next-generation nanoelectronics that can be fully integrated with silicon technology. To this day, the fabrication of Ge-based transistors with a n-type channel doping above 5 × 1019 cm−3 remains challenging. Here, we report on n-type doping of Ge beyond the equilibrium solubility limit (ne ≈ 6 × 1020 cm−3) together with a nanoscale technique to inspect the dopant distribution in n++-p junctions in GeOI. The n++ layer in Ge is realized by P+ ion implantation followed by millisecond-flashlamp annealing. The electron concentration is found to be three times higher than the equilibrium solid solubility limit of P in Ge determined at 800 °C. The millisecond-flashlamp annealing process is used for the electrical activation of the implanted P dopant and to fully suppress its diffusion. The study of the P activation and distribution in implanted GeOI relies on the combination of Raman spectroscopy, conductive atomic force microscopy, an...

The junctionless nanowire metal–oxide–semiconductor field-effect transistor (JNT) has recently been proposed as an alternative device for sub-20-nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS-compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain-induced-barrier lowering (DIBL) of 87 mV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A method for cross-sectional doping of individual Si/SiO2 core/shell nanowires (NWs) is presented. P and B atoms are laterally implanted at different depths in the Si core. The healing of the implantation-related damage together with the electrical activation of the dopants takes place via solid phase epitaxy driven by millisecond-range flash lamp annealing. Electrical measurements through a bevel formed along the NW enabled us to demonstrate the concurrent formation of n- and p-type regions in individual Si/SiO2 core/shell NWs. These results might pave the way for ion beam doping of nanostructured semiconductors produced by using either top-down or bottom-up approaches.

Hyperdoping consists of the intentional introduction of deep-level dopants into a semiconductor in excess of equilibrium concentrations. This causes a broadening of dopant energy levels into an intermediate band between the valence and conduction bands.[1,2] Recently, bulk Si hyperdoped with chalcogens or transition metals has been demonstrated to be an appropriate intermediate-band material for Si-based short-wavelength infrared photodetectors.[3-5] Intermediate-band nanowires could potentially be used instead of bulk materials to overcome the Shockley-Queisser limit and to improve efficiency in solar cells,[6-9] but fundamental scientific questions in hyperdoping Si nanowires require experimental verification. The development of a method for obtaining controlled hyperdoping levels at the nanoscale concomitant with the electrical activation of dopants is, therefore, vital to understanding these issues. Here, we show a CMOS-compatible technique based on non-equilibrium processing for the controlled doping of Si at the nanoscale with dopant concentrations several orders of magnitude greater than the equilibrium solid solubility. Through the nanoscale spatially controlled implantation of dopants, and a bottom-up template-assisted solid phase recrystallization of the nanowires with the use of millisecond-flash lamp annealing, we form Se-hyperdoped Si/SiO2 core/shell nanowires that have a room-temperature sub-band gap optoelectronic photoresponse when configured as a photoconductor device.

High-mobility materials and non-traditional device architectures are of key interest in the semiconductor industry because of the need to achieve higher computing speed and low power consumption. In this article, we present an integrated approach using directed self-assembly (DSA) of block copolymers (BCPs) to form aligned line-space features through graphoepitaxy on germanium on insulator (GeOI) substrates. Ge is an example of a high mobility material (III–V, II–VI) where the chemical activity of the surface and its composition sensitivity to etch processing offers considerable challenges in fabrication compared to silicon (Si). We believe the methods described here afford an opportunity to develop ultrasmall dimension patterns from these important high-mobility materials. High-quality metal oxide enhanced pattern transfer to Ge is demonstrated for the realization of nanofins with sub-10 nm feature size. Graphoepitaxial alignment of a poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) BCP was achieved using predefined hydrogen silsesquioxane (HSQ) topography at a GeOI substrate. Subsequent impregnation of the aligned BCP templates with a salt precursor in situ and simple processing was used to generate robust metal oxide nanowire (e.g., Fe3O4, γ-Al2O3, and HfO2) hardmask arrays. Optimized plasma based dry etching of the oxide modified substrate allowed the formation of high aspect ratio Ge nanofin features within the HSQ topographical structure. We believe the methodology developed has significant potential for high-resolution device patterning of high mobility semiconductors. We envision that the aligned Ge nanofin arrays prepared here via graphoepitaxy might have application as a replacement channel material for complementary metal–oxide–semiconductor (CMOS) devices and integrated circuit (IC) technology. Furthermore, the low capital required to produce Ge nanostructures with DSA technology may be an attractive route to address technological and economic challenges facing the nanoelectronic and semiconductor industry.

Supercritical resist drying allows the fabrication of high aspect-ratio (AR) resist patterns. The potential of this drying technique to increase the maximum achievable AR and the resolution of the overall lithographic process is analyzed for hydrogen silsesquioxane (HSQ). The maximum achievable AR is doubled compared to conventional nitrogen blow drying. Furthermore, the resolution is improved significantly.

Reactive ion etch (RIE) processes with HBr/O"2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12nm gate length and optimized photonic devices with ultrahigh Q-factors.

The surface roughness of hydrogen silsesquioxane (HSQ) as a negative tone electron beam (EB) resist has been studied as a function of exposure dose, developer concentration, and pre-exposure bake temperature. In the range of low exposure doses, the surface roughness of HSQ drops rapidly with an increase in the dose. It levels off at about 1 nm around the dose at which the respective contrast curve saturates. The TMAH developer concentration, varied in the range of 2.5–25%, has only a slight influence on the HSQ roughness. The increase of the baking temperature from 90 to 220 °C, however, causes a significant rise in the roughness of more than 100%. These results are discussed in terms of structural changes and network formation in thin HSQ films. They prove that a process combining high developer concentration and low baking temperature is preferable for fabrication of high resolution patterns using HSQ as a negative tone EB resist.

A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This ki ...

The integration of high-mobility III–V compound semiconductors emerges as a promising route for Si device technologies to overcome the limits of further down-scaling. In this work, we investigate the possibilities to form InAs nanocrystals in a thin Si layer at laterally defined positions with the help of masked ion beam implantation and flash lamp annealing. In detail, a cladding layer was deposited on a silicon-on-insulator (SOI) wafer and patterned by electron beam lithography in order to serve as an implantation mask. The wafer was subsequently implanted with As and In, followed by flash lamp annealing leading to the formation of InAs nanoparticles in the implanted areas. The structures were investigated by Raman spectroscopy, scanning, and transmission electron microscopy as well as energy-dispersive X-ray spectroscopy. Depending on the size of the implantation window, several, one or no nanoparticle is formed. Finally, the perspectives for using this technique for the local modification of Si nanowires are discussed.

3D vertically stacked silicon nanowire (SiNW) field effect transistors (FET) with high density arrays (up to 7×20) of fully depleted and ultra-thin (15–30 nm) suspended channels were fabricated by a top-down CMOS compatible process on silicon on insulator (SOI). The channels can be wrapped by conformal high-κ gate dielectrics (HfO 2 ) and their conductivity can be excellently controlled either by a reference electrode or by three local gates; a backgate (BG) and two symmetrical Pt side-gates (SG) offering unique sensitivity tuning. Such 3D structure has been (3-Aminopropyl)-triethoxysilane (APTES) functionalized and biotynilated for pH and streptavidin (protein) sensing, respectively. An ultra-low concentration of 17 aM of streptavidin was measured, the lowest ever reported in literature. Extremely high quasi-exponential drain current responses (ΔI d /pH) of ∼0.70 dec/pH were measured for structures with APTES functionalized SiO 2 gate dielectrics when operated in the subthreshold regime. Also, high drain current responses > 20 µA/pH and high sensitivities (S ∼ 95%) were measured for structures with a native oxide gate dielectrics when operated in the strong-inversion regime.

Top-down fabrication of sub-50nm silicon nanowire sensors with various geometries.Excellent performance as backgated junctionless nanowire transistors (JNTs).Very good sensing capabilities.Among the smallest top-down fabricated nanowire sensing devices reported to date. This article reports the fabrication of sub-50nm field effect transistor (FET)-type silicon (Si) nanowire (Si NW) chemical and biological sensing devices with a junctionless architecture, as well as on the initial characterisation of their electrical and sensing performance.The devices were fabricated using a fully complementary metal-oxide-semiconductor (CMOS)-compatible top-down process on silicon-on-insulator (SOI) wafers. The fabrication process was mainly based on high-resolution electron beam lithography (EBL) and reactive ion etching (RIE) but also included photolithography (mix-and-match lithography), thin film deposition by electron beam evaporation, lift-off, thermal annealing and wet etching.The sensing performance of a matrix of nanowire devices, i.e. containing 1, 3 and 20 NWs with lengths of 0.5, 1 and 10µm was examined. Each element of the matrix also contained five devices with different NW widths: 10, 20, 30, and 50nm and 5µm (a Si belt reference device). Electrical characterisation of the devices showed excellent performance as backgated junctionless nanowire transistors (JNTs): high on-currents in the range of 1-10µA and high ratios between the on-state and off-state currents (Ion/Ioff) of 6-7 orders of magnitude. In addition, the results of ionic strength sensing experiments demonstrate the very good sensing capabilities of these devices. To the best of our knowledge, these nanowire sensors are among the smallest top-down fabricated Si NW devices reported to date.

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high I on /I off current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published.

A micro-power energy harvesting system based on core(crystalline Si)-shell(amorphous Si) nanowire solar cells together with a nanowire-modified CMOS sensing platform have been developed to be used in a dust-sized autonomous chemical sensor node. The mote (SiNAPS) is augmented by low-power electronics for power management and sensor interfacing, on a chip area of 0.25mm(2). Direct charging of the target battery (e. g., NiMH microbattery) is achieved with end-to-end efficiencies up to 90% at AM1.5 illumination and 80% under 100 times reduced intensity. This requires matching the voltages of the photovoltaic module and the battery circumventing maximum power point tracking. Single solar cells show efficiencies up to 10% under AM1.5 illumination and open circuit voltages, Voc, of 450-500mV. To match the battery's voltage the miniaturised solar cells (similar to 1mm(2) area) are connected in series via wire bonding. The chemical sensor platform (mm 2 area) is set up to detect hydrogen gas concentration in the low ppm range and over a broad temperature range using a low power sensing interface circuit. Using Telran TZ1053 radio to send one sample measurement of both temperature and H-2 concentration every 15 seconds, the average and active power consumption for the SiNAPS mote are less than 350nW and 2.1 mu W respectively. Low-power miniaturised chemical sensors of liquid analytes through microfluidic delivery to silicon nanowires are also presented. These components demonstrate the potential of further miniaturization and application of sensor nodes beyond the typical physical sensors, and are enabled by the nanowire materials platform.

The influence of megasonic agitation on the development of nanostructures with high aspect ratio is investigated thoroughly. The improvements in homogeneity, depth, and quality of nanostructures are related to specific interactions of the sound wave with the resist and developer. Two phases in the development process are operative. The specific role of microstreaming providing physical supply of fresh developer is identified and the reduction of viscosity by megasonic interaction is derived. The advantage of megasonic agitation as a nondestructive development of high aspect ratio nanostructures is demonstrated.

Germanium is a promising high-mobility channel material for future nanoelectronic devices. Hydrogen silsesquioxane (HSQ) is a well known high-resolution electron beam lithography (EBL) resist, which is usually developed in aqueous based developers. However, this feature of HSQ causes troubles while patterning Ge surface as it is always shielded with native Ge oxides. GeO2 is a water soluble oxide, and since HSQ resist is developed in aqueous solvents, this oxide interferes with the patterning. After the EBL exposure, GeO2 is washed off during the development, lifting the patterned structures and making the high-resolution patterning impossible. To avoid this issue, it is necessary to either clean and passivate the Ge surface or use buffer layers between the native Ge oxides and the HSQ layer. In this article, a novel technique to clean the Ge surface prior to HSQ deposition, using simple “household” acids like citric acid and acetic acid, is reported. The acids are able to remove the native Ge oxides as w...

A high-gain photodetector based on junctionless MOSEFT has been presented in this work. Tri-gate junctionless nanowire phototransistors were fabricated on (100) silicon-on-insulator wafers with a buried oxide of thickness 145 nm and top silicon layer of thickness 10 nm. The gate stack consisted of a 10 nm SiO2 dielectric and a 50 nm poly-Si gate electrode. The channel length and doping concentration of junctionless n-MOSFETs was 1 μm and 3 × 1019 cm−3, respectively. The dark current of this device measured at room temperature was less than 1 pA. The measured internal gain of the device was about 35 for 860 nm light illumination. The photocurrent was 300 times larger than the dark current for only 30 nW incident power on the nanowire at 300 mV drain bias.

A single step metal assisted etching (MAE) process, utilizing metal ion-containing HF solutions in the absence of an external oxidant, has been developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. Detailed characterisation of both the porous and non-porous sections of the Si nanowires was provided by transmission electron microscopy studies, enabling the mechanism of nanowire roughening to be ascertained. The versatility of the MAE method for producing heterostructured Si nanowires with varied and controllable textures is discussed in detail.

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.

An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si 3 N 4 ) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.