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Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~1010. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe2 p−n homojunction. The WSe2 FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe2 FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%. [ABSTRACT FROM AUTHOR]

The pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months. [ABSTRACT FROM AUTHOR]

Achieving low contact resistance (RC) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate‐voltages (VTG and VBG). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG, in sharp contrast to Ti contacts that only modulate RC by varying VBG. The anomalous behavior is attributed to the strongly modulated pseudo‐junction resistance (Rjun) by VTG, resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG. Technology computer aided design simulations further confirm the contribution of VTG to Rjun, which improves overall RC of Sb‐contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual‐gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG. The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals. [ABSTRACT FROM AUTHOR]

Even though atomically thin 2D semiconductors have shown great potential for next‐generation electronics, the low carrier mobility caused by poor metal–semiconductor contacts and the inherently high density of impurity scatterings remains a critical issue. Herein, high‐mobility field‐effect transistors (FETs) by introducing few‐layer PdSe2 flakes as channels is achieved, via directly depositing semimetal antimony (Sb) as drain–source electrodes. The formation of clean and defect‐free van der Waals (vdW) stackings at the Sb–PdSe2 heterointerfaces boosts the room temperature transport characteristics, including low contact resistance down to 0.55 kΩ µm, high on‐current density reaching 96 µA µm−1, and high electron mobility of 383 cm2 V−1 s−1. Furthermore, metal–insulator transition (MIT) is observed in the PdSe2 FETs with and without hexagonal boron nitride (h–BN) as buffer layers. However, the layered h–BN/PdSe2 vdW stacking eliminates the interference of interfacial disorders, and thus the corresponding device exhibits a lower MIT crossing point, larger mobility exponent of γ ∼ 1.73, significantly decreased hopping parameter of T0, and ultrahigh electron mobility of 2,184 cm2 V−1 s−1 at 10 K. These findings are expected to be significant for developing high mobility 2D‐based quantum devices. [ABSTRACT FROM AUTHOR]

Recently, 2D materials have been intensively investigated for their novel nanoelectronic applications; among these materials, tungsten diselenide (WSe2) is attracting substantial research interest due to its high mobility, sizable bandgap, and ambipolar characteristics. However, Fermi‐level pinning (FLP) at the metal–semiconductor contact is a critical issue preventing further integration of WSe2 to complementary metal–oxide–semiconductor (CMOS) technology. In this study, a facile doping method of oxygen (O2) plasma treatment and an aging effect to overcome the FLP of WSe2 field‐effect transistors (FETs) are utilized. After aging, a reduction is observed in FLP on oxidized WSe2 FETs, along with a decrease in pinning factor (S) for holes from −0.06 to −0.36. Further, the field‐effect mobility of high‐ (Pd) and low‐ (In) work‐function contacted WSe2 devices indicates the presence of more improvement in high‐work‐function metal‐contacted p‐type WSe2 FETs, which further strengthens the Fermi level de‐pinning behavior attributed to the O2 plasma and aging processes. The existence of different tunneling behaviors of Pd and In devices also confirms the effect of O2 plasma doping into WSe2 FETs. Ultimately, this work demonstrates a simple and efficient method for achieving the de‐pinning of Fermi‐levels and modulating FLP of 2D FETs. [ABSTRACT FROM AUTHOR]