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Watt’s nickel bath and nickel sulfamate bath are commonly applied for plating of micro-fabrication parts. In particular, the nickel sulfamate bath produces nickel plating with low residual stress and high tensile strength. Nickel sulfamate baths are therefore used extensively for electroforming and Micro Electro Mechanical Systems (MEMS). Boric acid is usually used as a pH buffering agent in the plating bath. However, boron-containing effluents are increasingly regulated because of environmental concerns. To solve these problems, organic acids such as acetic acid and citric acid were investigated as alternatives to boric acid. The pH buffering action of the organic acid baths was higher than that of the boric acid bath. Furthermore, the mechanical properties of nickel films obtained from a low-concentration nickel plating bath using an organic acid buffer were superior to those obtained from a bath buffered with boric acid. Nickel films with good mechanical properties were obtained from high-concentration nickel baths, which showed good pH stability even without a buffering agent in the formulation. Subsequent SEM and XRD analyses of these plating films revealed a defect free cantilever structure prepared with MEMS.

銅めっきによるビアフィリングは，プリント配線板や三次元実装に広く使われている。電気銅めっきによるビアフィリングは，促進剤や抑制剤などの添加剤を用い，すでに検討されている。ビアフィリングの埋め込みメカニズムは，いくつか提案されている。しかしながら，ビアホールにおけるめっきの結晶成長は，詳細に検討されていない。本論文では，ビアホールの埋め込み過程を経時的に観察する方法やめっきの結晶組織の観察を行った。めっきの結晶方位測定は後方散乱電子線回折装置，結晶形態は透過型電子顕微鏡により分析した。多層めっきやパルスめっきにより，ホール上部ではめっき析出が抑制，底部では促進され，ビアフィリングのめっき成長過程を観察することができた。無電解ニッケルめっき層を挿入する方法では，フィリング性に変化が出てしまうのに対して，短時間のパルスめっきを挿入する方法では，フィリング性や結晶成長に大きな影響を与えることなくめっき成長の途中経過を観察できた。

Recently high-density packaging technologies have been in strong demand in an effort to realize the ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmentally-friendly packaging. The purpose of this study is to propose a fabrication method for a multichip module system using W-CSP technology. In this study, we fabricated a two-chip module with W-CSP using an excimer laser to form via-holes and electro-plating to fill the via-holes. This study has two main new technologies: one is new via-hole formation using an excimer laser that makes small (30 μm diameter) and deep (50 and 100 μm) via-holes, with a micro-lens array used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. The second new technology is new copper electroplating techniques to fill the via-holes which have same diameter (30 μm) and different depths (50 and 100 μm) by controlling additives and agitating conditions. In this study, we fabricated a two-chip module, and both chips were covered by resin simultaneously. The second chip, whose thickness was 50 μm, was mounted on a wafer (first chip) after the first chip had completed the wafer process. The second chip was thinned and mounted by die attachment film (DAF). Next, the mounted chips were spin-coater with polyimide or epoxy resin about 100 μm in thickness. Two types of via-hole with different depths, 50 and 100 μ m, were formed by excimer laser to connect the wafer and mounted chip pads. Both types of via-hole had a diameter of about 30 μm. After via-hole formation, seed layers, sputtered Ti and Cu films, are necessary for subsequent copper electro-deposition. Using microscopy measurement, the seed layers were seen to be uniformly formed from the top to the bottom of the via-hole. Using a general mixture of additives, brightener, leveler, and suppressor, the via-holes were completely filled. By controlling the suppressor effect, the 100 μm deep via-holes were perfectly filled with the copper electroplating. Both mechanical agitation and current density are effective to ensure via-hole filling and optimization of these two factors is very important in filling via-holes. Moreover, an additional electroless copper seed layer to increase conductivity near the bottom of the via-hole is also effective to suppress voids there. Finally, the conductivities between the first and second chips were confirmed for the multi-chip module fabricated using W-CSP with excimer laser and copper electro-plating.

A multi-chip module (MCM) was fabricated using an excimer laser driller and electro-plating. This method contributes to the interconnection properties of the MCM. First, a second chip with a thickness of 50 μm was mounted on a wafer that had been created by a wafer process, and polyimide with a thickness of about 100 μm was applied by a spin-coater to cover the mounted chips. Two types of via-holes, with depths of 50 and 100 μm, were formed by the excimer laser to connect the wafer and mounted chip pads. The excimer laser driller with a micro-lens array formed two types of via with diameters of about 30 μm simultaneously. Damage caused by the excimer laser irradiation was examined by direct laser irradiation of the FET transistor gate. Properties of the FET transistor did not change even after 500 pulses of 400 mJ/ cm 2 which is sufficient for via-hole formation. A micro-lens array was designed to shorten the via-hole formation time. After via-hole formation, a seed-layer of sputtered Ti and Cu films were necessary, followed by copper electro-deposition. Microscopy measurements confirmed that the seed-layers were uniformly formed from top to bottom of the via-hole. Generally the mixture of additives to complete the via-hole filling consists of brightener, leveler, and a suppressor. By controlling the leveler concentration, a via-hole with a diameter of 30 μm and a depth of 100 μm was perfectly filled by copper electroplating. In this way the multi-chip module was created by wafer-level chip size technologies (W-CSP) using an excimer laser driller.

Our previous studies showed that co-deposition of refractory metal improves the properties of Ni–P films, so in this study we examined electroless Ni–W–P and Ni–Mo–P alloy films as alternatives to Pd films. High heat-resistance is necessary in the intermediate layer of printed wiring boards. The ternary Ni alloy films exhibit high heat-resistance properties. These new intermediate layers were evaluated from the viewpoint of wire-bonding strength. Results indicate that the new intermediate layers have almost the same properties as Pd intermediate layers and lamination. The experimental results also show that the ternary Ni alloy films suppress local corrosion, and Ni diffuses to the Au surface in the same way as a Pd intermediate layer.

An improved method for connecting flexible printed circuits and indium tin oxide (ITO) electrodes is proposed in this paper. The adhesives used were composed of a thermosetting resin and a thermoplastic resin. The test sample consisted of a polyimide base flexible printed circuit, (FPC). Non-conductive film (NCF) was pre-laminated on an ITO-glass and the test sample was then thermally bonded to the glass. The contact resistance between the ITO-glass and FPC was measured by a 4-probe method. A Cu wiring on the FPC was chemically etched, followed by selective electroless Ni–P deposition using hydrazine and sodium hypophosphite as reducing agents; Au film was then plated onto it. Since this method does not create extraneous deposition, it is one of the most promising candidates for future fine connection manufacturing processes. With lines and spaces of 75 μm and 75 μm, insulation resistance of 1 × 108 Ω remained constant at 60 °C, 90 %RH, 30 V for 60 hours. Various FPCs with different line and space combinations have been investigated by the same method. The lines and spaces of 15 μm and 25 μm, 20 μm and 20 μm, and 25 μm and 15 μm show contact resistance of 2.02 Ω, 1.26 Ω and 0.844 Ω, respectively. Therefore, this method is intrinsically suitable for fine pitch FPCs with high reliability.

Boric acid is generally added to buffer the pH and improve the life expectancy of a nickel plating bath. The plating industry has requested alternatives to boric acid because its use will be restricted in the future. In this study, the hull cell, pH buffer correlation and cathode current efficiency tests were conducted using 21 different substitute buffering agents. From these 21 agents, acetic acid, propionic acid, nickel acetate and citric acid showed the same appearance and buffering ability as boric acid. Physical properties, such as Vickers hardness, tensile strength and internal stress test were measured on nickel samples made using these four buffering agents, as well as boric acid. When using these four organic compounds, the internal stress somewhat higher compared with a standard boric acid bath, but the other physical properties were almost all the same, except in the case of citric acid. It was found that citric acid produced samples with higher Vickers hardness. For all the buffers, as current density increased, Vickers hardness decreased and tensile strength increased. The physical properties of samples made with these buffers show the same trends vs. current density as those made with boric acid bath.

Recently high density packaging technologies have been strongly requested to realize ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmental friendly packaging. Purpose of this study is to fabricate system in package (SiP) by using W-CSP technology. In this study, we have fabricated two chip module by W-CSP using excimer laser to form via-holes and electro-plating to fill via-holes. This study has two main new technologies, one is new via-hole formation by using excimer laser that makes small (30µm diameter) and deep (50 and 100µm) via-holes, a micro-lens array has been used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. And the other is new copper electroplating techniques to fill via-holes which have same diameter (30µm) and different depth (50 and 100µm) by controlling additives and agitating conditions. In this study, we have fabricated two chip module, first step, second chip mounting on first chip. The second chips whose thickness was 50 µm was mounted on wafer (first chip) that has been finished up wafer process. The second chips have been thinned and mounted by DAF tape. Next, polyimide or epoxy resin whose thickness was about 100 µm was coated by spin-coater to cover the mounted chips. Two types of viahole whose depths were different, 50 and 100 µm, should be formed by excimer laser to connect pads between the wafer pad and mounted chip pad. The excimer laser have formed two types of via whose diameter was about 30 µm. Damage by excimer laser irradiation have been examined by irradiation of laser to gate of FET transistor directly. Properties of FET transistor did not change even after 500 pluses of 400 mJ/cm2 which are much enough for via-hole formation. To shorten via-hole formation time, a micro-lens array was designed. An ashing process with CF 4 gas has performed to clean surface and inside of via-holes. After via-hole formation, seed-layers, sputtered Ti and Cu films are necessary for following copper electro-deposition. By microscopy measurement, the seed-layers were uniformly formed from top to bottom of via-hole. In general mixture of additives, these are brightener, leveler and suppressor, made via-hole filling completely. By controlling leveler effect, the via-hole with 30 µm diameter and 100 µm depth have been perfectly filled by copper electroplating. Both mechanical agitation and current density is effective to via-hole filling. Moreover, additional electroless copper seed-layer to increase conductivity at near the bottom of via-hole is also effective to suppress voids at the bottom of vai-holes. Therefore, the multi-chip module would be performed by the W-CSP with excimer laser and copper electro-plating.

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