565 results on '"Yin, Huaxiang"'
Search Results
2. An AND-type 1T-FeFET array with robust write and read operations
3. Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs
4. Design and testing of LGAD sensor with shallow carbon implantation
5. Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance
6. Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors
7. Hybrid simulation method of quantum characteristics for advanced Si MOSFETs under extreme conditions by incorporating simplified master equation with TCAD
8. Effects of shallow carbon and deep N++ layer on the radiation hardness of IHEP-IME LGAD sensors
9. Low Gain Avalanche Detectors with Good Time Resolution Developed by IHEP and IME for ATLAS HGTD project
10. Leakage current simulations of Low Gain Avalanche Diode with improved Radiation Damage Modeling
11. Recent progress of hafnium oxide-based ferroelectric devices for advanced circuit applications
12. Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors
13. Ultra-high voltage silicon pixel sensor with less soft-breakdown for X-ray free electron laser
14. Heteroepitaxy of semiconducting 2H-MoTe2 thin films on arbitrary surfaces for large-scale heterogeneous integration
15. Discussion of “From experiment to the field: The case of a price formation model based on laboratory findings”
16. Simulation of silicon quantum dots with diamond-channel by simplified ME model
17. Low-temperature (≤550 °C) p-channel Schottky barrier SOI FinFETs for monolithic 3D integration
18. Integrated Extraction of Root Diameter and Location in Ground-Penetrating Radar Images via CycleGAN-Guided Multi-Task Neural Network.
19. Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current
20. Improved Subthreshold Characteristics by Back-Gate Coupling on Ferroelectric ETSOI FETs
21. Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance
22. Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process
23. The Investigation of Reduced Variation Effect in FinFETs With Ultrathin 3-nm Ferroelectric Hf₀.₅Zr₀.₅O₂
24. Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit
25. High-Performance GAA FETs With 100 Ω Parasitic Resistance and 965 μA/μm On-State Current Using Quasi-Self-Aligned Landing Pads
26. Realization of Steep-Slope Transistor Using 1-D Gate-All-Around Carbon Nanotubes With Broken-Gap Source Structure
27. Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
28. High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications
29. Accumulative total ionizing dose (TID) and transient dose rate (TDR) effects on planar and vertical ferroelectric tunneling-field-effect-transistors (TFET)
30. Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal
31. Experimental study of the ultrathin oxides on SiGe alloy formed by low-temperature ozone oxidation
32. O2 plasma treated biosensor for enhancing detection sensitivity of sulfadiazine in a high-к HfO2 coated silicon nanowire array
33. Unique Consecutive RTN Characteristics Coupled With Ferroelectric Nanodomain Switching in Advanced Fe-FinFETs
34. Ultra-large scale array silicon pixel sensors with uniform and low leakage current for advanced X-ray light sources
35. Investigation of Electrical Characteristics of a Fabricated Lgad Detectors at High and Low Temperatures
36. Interface Treatment of Epitaxial SI FINFET Channel in Replace Metal Gate with Simultaneously Performance Improvement and Leakage Reduction
37. Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding
38. Impact of Thickness Dependent Ferroelectric and Interface Charge Variation on Device-to-Device Variation in Ferroelectric FET
39. Ultrasensitive 3D Stacked Silicon Nanosheet Field-Effect Transistor Biosensor with Overcoming Debye Shielding Effect for Detection of DNA
40. The optimization of contact interface between metal/MoS2 FETs by oxygen plasma treatment
41. Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device
42. High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer
43. Quantum transport for gate length scaling limit of Si NWFETs based on calibrated k·p Hamiltonian parameters
44. Hybrid Simulation Method of Quantum Characteristics for Advanced Si Mosfets Under Extreme Conditions by Incorporating Simplified Master Equation with Tcad
45. Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond
46. First Demonstration of True 4-bit Memory with Record High Multibit Retention >103s and Read Window >105 by Hydrogen Self-Adaptive-Doping for IGZO DRAM Arrays
47. Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm
48. The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks
49. Leveling the Playing Field : The Selection and Motivation Effects of Tournament Prize Spread Information
50. Influence of the hard masks profiles on formation of nanometer Si scalloped fins arrays
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.