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In this article, a 4H-SiC metal-insulator-semiconductor-insulator-metal (MISIM) ultraviolet (UV) photodetector (PD) with a normal working temperature up to 550 °C, has been successfully fabricated and characterized for the first time. At 550 °C, the dark current of our fabricated MISIM remains at ~0.2 nA level and a record photo-to-dark current ratio (PDCR) of 62.7 is achieved at a reverse bias voltage of −15 V. Under 275 nm illumination, high responsivity (R) of 0.23 and 0.54 A/W have been achieved at room temperature (RT) and 550 °C, respectively. To the best of our knowledge, this is the best result reported for high-temperature UV detectors based on the 4H-SiC. This work is significant for developing high-temperature 4H-SiC-based UV PDs.

The reverse breakdown characteristics of 4H-SiC Junction Barrier Schottky (JBS) rectifiers adopting the different floating limiting rings (FLRs) termination structures are experimented and analyzed under the repetitive avalanche current stress. The experimental results indicate that the breakdown voltage (BV) shift of the device after the repetitive avalanche current stress is highly dependent on the FLRs design, which determines the distributions of the surface electric field and avalanche current at avalanche condition. It is proved that the uniform surface electric field distribution of the FLRs structure at avalanche condition is helpful for the device achieve to achieve better BV shift robustness on the repetitive avalanche current stress. Additionally, the FLRs structure, which has smaller S1 and enough Nr, can present both higher BV and excellent BV shift robustness on the repetitive avalanche current stress.

In this article, a novel planar InAs/GaSb heterojunction face-tunneling FET (HFTFET) is proposed for device performance improvement. As is known in previous studies, the entire tunneling junction of HFTFET can be controlled by gate effectively and uniformly, and therefore, the large effective tunneling area and extremely steep turn on/off switch would be achieved. However, the leakage current between source and drain degrades the OFF-state characteristics and turn on/off switch greatly. Hence, an implanted drain is introduced in the proposed InAs/GaSb HFTFET for reducing the leakage to optimize the performance, which also makes the fabrication process compatible with the standard CMOS process platform. Consequently, large tunneling current, steep subthreshold swing, and small leakage current can be obtained simultaneously, which would further promote the development of tunnel field-effect transistors (TFETs) and their ultralow-power applications.

As a promising ultra-wide bandgap semiconductor, the β-phase of Ga 2 O 3 has attracted more and more interest in the field of power electronics due to its ultra-wide bandgap (4.8 eV), high theoretical breakdown electric field (8 MV/cm), and large Baliga's figure of merit, which is deemed as a potential candidate for next generation high-power electronics, including diodes, field effect transistors (FETs), etc. In this article, we introduce the basic material properties of Ga 2 O 3 , and review the recent progress and advances of β-Ga 2 O 3 based metal-oxide-semiconductor field-effect transistors (MOSFETs). Due to the problematic p-type doping technology up to now, the enhancement-mode (E-mode) β-Ga 2 O 3 FETs face more difficulties, compared with depletion mode (D-mode). This article focuses on reviewing the recent progress of E-mode Ga 2 O 3 MOSFETs, summarizing and comparing various feasible solutions when p-type doping is absent. Furthermore, the device fabrication and performances of state-of-art β-Ga 2 O 3 MOSFETs, including D-mode, E-mode, and planar/vertical structure are fully discussed and compared, as well as potential solutions to the challenges of Ga 2 O 3 FETs.

As the p-type doping $\beta $ -Ga2O3 is absent up to now, metal gate (MG) stacks with high work functions are expected to benefit the fabrication of normally- OFF $\beta$ -Ga2O3 transistors. In this article, the electrical characteristics of $\beta $ -Ga2O3 metal-electrode-gated metal–oxide–semiconductor (MOS) devices with Al-rich HfAlO dielectrics and different MG stacks (Ni, Au, Pt, and Ti) are evaluated. The interface state density ( ${D}_{\text {it}}$ ) of HfAlO/ $\beta $ -Ga2O3 interface is characterized based on the frequency-dependent capacitance–voltage ( ${C}{-}{V}$ ) and photo-assisted deep ultraviolet (DUV) ${C}{-}{V}$ measurements. An average $D_{\text {it}}$ of ${4.45}\times {10}^{{11}}$ eV $^{-{1}}$ cm $^{-{2}}$ is extracted from the photo-assisted (deep UV) ${C}{-}{V}$ measurement, while a large amount of border traps, negative fixed charges, and deep traps is also induced at the oxide layer and/or HfAlO/ $\beta $ -Ga2O3 interface. Then, this article investigates the evaluations of Ti, Ni, Au, and Pt as candidate MGs for $\beta $ -Ga2O3 MOS using Al-rich HfAlO as gate dielectric. The obvious flat-band voltage ( $V_{\text {FB}}$ ) shift and gate leakage variation are observed in $\beta $ -Ga2O3 capacitors with different MG solutions, indicating that HfAlO dielectric combined with Ni, Au, and Pt MGs is promising to facilitate some beneficial modifications of normally- OFF $\beta$ -Ga2O3 transistors, while Ti electrode is more suitable for normally- ON $\beta$ -Ga2O3 transistors. This article provides an additional practical guideline for choosing the appropriate MG stacks and potential gate dielectric to the development of normally-OFF Ga2O3 transistors.

In this letter, we present a 24-GSa/s, >20-GHz wideband track-and-hold amplifier (THA) based on indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology for high-speed sampling systems. In the proposed approach, the output pole of the input stage is canceled by the zero produced by the emitter capacitive/resistive degeneration, and the bandwidth is thereby extended without voltage drop. The compensation technique for $V_{\mathrm{be}}$ modulation in the output stage is introduced to reduce distortion. The monolithic microwave integrated circuit (MMIC) prototype occupies only 0.69 mm2, and the experimental results show that it has a 0.112– $f_{T}$ bandwidth from dc to 22.3 GHz, which is wider than any ratio reported compact THA solutions using the InP technology. In addition, a spurious-free dynamic range (SFDR) of better than 42 dB and total harmonic distortion (THD) of less than −25 dBc are demonstrated at a 24-GSa/s sampling rate. The THA consumes only 374 mW, which is among the lowest dc power dissipation reported for the InP technology.

This paper reports the demonstration of a high performance 4H-SiC floating junction junction barrier Schottky (FJ_JBS) rectifier with a 30μm, 6×1015 cm-3-doped epitaxial layer. Extensive simulations have been performed to design, optimize and analyze the structure of the FJ_JBS rectifier. The fabricated FJ_JBS shows that breakdown voltage (BV) and differential Ron,sp are 3.4 kV, yielding the highest BV value reported for 4H-SiC FJ diodes, and 5.67 mΩ·cm2, respectively. Compared with the conventional JBS, the BV value of FJ_JBS increases by 33.3% and the Ron,sp only slightly rises by 6.2%. The corresponding Baliga figure-of-merit (BFOM) (4 BV2/Ron_sp) of this FJ_JBS diode is 8.16 GW/cm2.

A novel 4H-SiC multizone collector vertical insulated-gate bipolar transistor (MZC-IGBT) with an alternate P+/P−/P+ multizone structure in the collector region is proposed and investigated by numerical simulations in this article. Comparing with conventional 4H-SiC IGBTs, lower potential barrier regions are formed in the proposed MZC-IGBT at the interface between the N field-stop buffer and the collector region, modifying the carrier extraction effect to a proper level and resulting in a superior tradeoff between the static and dynamic performances. The proposed device consumes less energy in a wide frequency range. The numerical simulation reveals that the average dissipation power of the optimized 4H-SiC MZC-IGBT can be decreased by 63.1% at a high frequency of 20 kHz and even 2.26% at a low frequency of 500 Hz, which makes the proposed device much more suitable for high-frequency applications.

The properties of 4H–SiC/Ni/Ti/Al/W metal contacts on n-type and p-type ion-implanted 4H–SiC layers are studied in this paper, with the aim of realizing simultaneous ohmic contact formation. The thickness of the Al film and the alloying temperature are analyzed. Specific contact resistances of 8 × 10−4 Ω cm2 and 4.1 × 10−5 Ω cm2 were achieved with multi-metal layer Ni/Ti/Al/W (80/30/110/50 nm) for n-type and p-type 4H–SiC, respectively, at an annealing temperature of 750 °C. This is for first time at such a low annealing temperature that ohmic contacts have been reported to simultaneously form on n-type and p-type 4H–SiC with satisfactory specific contact resistances. Samples were characterized using AFM, XRD, AES and TEM, and the results indicate that the presence of the W top layer facilitates lowering the surface roughness and accumulating elemental Ni and Al on the SiC side during annealing, which benefits the formation of the ohmic contacts.

The effect of traps to C–V and I–V plots of InP/InGaAs heterostructure with 3 MeV proton irradiation at different fluences has been discussed. After proton irradiation, the total reverse capacitanc...

NO post-oxidation annealing (POA) processes with different temperatures and durations are simultaneously studied on the n-type and p-type 4H-SiC MOS capacitors. The results from Secondary Ion Mass Spectroscopy (SIMS) reveal that nitrogen diffuses further into the SiO2 layer for the samples annealed at higher temperature (1250 °C). Furthermore, the area densities of nitrogen for the n-type samples are about 1.3 times larger than the p-type samples. The densities of negative effective fixed dielectric charge (Neff) and slow-state electron traps are effectively decreased with increasing annealing time and temperature for the n-type samples. However, the introduced nitrogen leads to more the deep energy-level traps [0.5–0.6 eV above the valence band edge (Ev)] in the p-type samples, which can exchange electrons with near-interface traps in response to the alternating current (AC) signal below 10 kHz. Besides, the densities of the slow-state hole traps, which are obviously increased at low temperature but raised slowly at high temperature, are mainly affected by the temperature of the NO POA process and not only the density of incorporated nitrogen. Therefore, NO annealing at high temperature with a short duration (at 1250 °C 1 h) may be a good choice to optimize NO POA treatment for n-channel 4H-SiC MOSFETs, based on comprehensive consideration of the influence of different NO POA conditions on n-type and p-type MOS capacitors.