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In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

The reliability of the resistor-capacitor (RC) time constant of a continuous-time (CT) filter has long been an obstacle with integrated circuits. Due to process and temperature variations in complementary metal-oxide semiconductor (CMOS) technology, the absolute value of the RC time constant may vary over ±50%, which is a big issue for many integrated continuous-time analog circuits. This study proposes an on-chip RC time constant auto-tuning scheme. The proposed scheme is based on the discrete master–slave auto-tuning concept. Considering the limitations in conventional works, a higher tuning accuracy is achieved by adopting two techniques: firstly, parasitic capacitance cancelation is proposed to eliminate the effects caused by parasitic capacitance; secondly, symmetric comparison is introduced to minimize the influence of the DC offset of the comparator. A successive approximation procedure is applied to improve the tuning speed. The proposed auto-tuning scheme has been validated in 55 nm CMOS technology with a fourth-order active-RC low-pass filter under PVT variations and 60 mV input offset voltage. The average tuning error is 2.21%, and the maximum error is 3.67%. The tuning error of the proposed scheme is considerably lower than the conventional scheme.

Abstract This study presents a 4.6–12.8 GHz injection‐locked frequency divider (ILFD) based on modified varactor‐less Colpitts oscillator topology. A modified Colpitts ILFD is proposed to improve the LR and reduces power consumption, simultaneously. Meanwhile, the forward body bias technique is utilized to further decrease power consumption. Based on the 55 nm CMOS technology, a modified varactor‐less Colpitts ILFD with a free‐running frequency of 4.05 GHz is implemented. The proposed modified varactor‐less Colpitts ILFD exhibits 94.3% LR from 4.6 to 12.8 GHz with an injection power of 0 dBm. It consumes 2.7 mW power from 0.6 V supply voltage and the core area is 0.38 mm2.

In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-NSFET) as a label-free biosensor has been proposed and investigated. The influences of different biomolecules on the biosensor’s electrical properties are analyzed, and the proposed biosensor exhibits good sensitivity for both neutral and charged biomolecules. Furthermore, a deep sensitivity analysis is performed to evaluate the sensing ability of biosensors with different channel structures. The sensitivity variation of biosensors is analyzed in terms of subthreshold swing ( $SS $ ), threshold voltage ( $V_{\text {th}}$ ), and current switching ratio ( $I_{\text {on}} / I_{\text {off}}$ ). The results show that GAA-NSFET-based biosensor obtains the best sensitivity compared with other biosensors (including nanowire FET-based biosensor and vertically stacked nanowire FET-based biosensor) due to its larger channel width and multi-channels. Also, the influences of filling position on sensitivity are analyzed in various cases for the proposed biosensor. Its sensitivity depends on the filling amounts of biomolecules instead of the filling position. Finally, a status map is presented, which plots the sensitivity of some important works in biosensing application along with the sensitivity of the proposed biosensor, and GAA-NSFET-based biosensor is more sensitive compared with those works in terms of $I_{\text {on}}/I_{\text {off}}$ sensitivity.

On-orbit space technology is used for tasks such as the relative navigation of non-cooperative targets, rendezvous and docking, on-orbit assembly, and space debris removal. In particular, the pose estimation of space non-cooperative targets is a prerequisite for studying these applications. The capabilities of a single sensor are limited, making it difficult to achieve high accuracy in the measurement range. Against this backdrop, a non-cooperative target pose measurement system fused with multi-source sensors was designed in this study. First, a cross-source point cloud fusion algorithm was developed. This algorithm uses the unified and simplified expression of geometric elements in conformal geometry algebra, breaks the traditional point-to-point correspondence, and constructs matching relationships between points and spheres. Next, for the fused point cloud, we proposed a plane clustering-method-based CGA to eliminate point cloud diffusion and then reconstruct the 3D contour model. Finally, we used a twistor along with the Clohessy–Wiltshire equation to obtain the posture and other motion parameters of the non-cooperative target through the unscented Kalman filter. In both the numerical simulations and the semi-physical experiments, the proposed measurement system met the requirements for non-cooperative target measurement accuracy, and the estimation error of the angle of the rotating spindle was 30% lower than that of other, previously studied methods. The proposed cross-source point cloud fusion algorithm can achieve high registration accuracy for point clouds with different densities and small overlap rates.

We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate- (DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitor Cgd for n-type TFETs with donor-like and acceptor-like ITs.

This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current. It is found that this structure can offer four tunneling junctions by increasing a source region. Meanwhile, the dual source structure does not influence the excellent features of threshold slope (SS) of TFET. The number of the electrons and holes would be doubled by going through the tunneling junctions on the original basis. The overlap length of gate-source is also studied. The dependence of gate-drain capacitance Cgd and gate-source capacitance Cgs on gate-to-source voltage Vgs and drain-to-source voltage Vds was further investigated. There are simulation setups and methodology used for the dual source TFET (DS-TFET) assessment, including delay time, total energy per operation, and energy-delay product. It is confirmed that the proposed TFET has strong potentials for VLSI.