Search

For the first time, we have demonstrated the reliability degradation of gate dielectric due to contamination of chromium in the silicon substrate. Before semiconductor processing, it is difficult to detect the chromium in bare wafer because the Cr-ion is quite low concentration and stable in the Si-sub. Combining time-dependent dielectric breakdown (TDDB) test with Secondary Ion Mass Spectrometer (SIMS) analysis, it performed that the drastically increasing of Cr-ion concentration in the gate oxide during thermal oxidation which decreased the lifetime of TDDB because chromium tends to oxidize and then becomes charged trap in gate oxide. Therefore, the control of Cr-ion concentration is important to increase the gate oxide reliability during semiconductor fabrication.

In this paper, we investigated SACVD O3-TEOS USG, BPSG, PSG and PECVD PSG films as sacrificial layers to formation a fluid tank with a fluid barrier layer in a micro-fluid dispenser device. The wet etch rate of as deposited films was measured and the SACVD PSG film performed with the highest wet etch rate as 5913A/min in a 6:1 buffered oxide etch solution. Inversely, the SACVD BPSG film displayed a lowest wet etch rate as 1650A/min in comparison with other sacrificial materials above. In the process integration consideration, patterned wafer with stacking sacrificial layers and fluid barrier layers were fabricated, then the sacrificial layer etched out in HF solution. Based on the microscopic view the SACVD PSG film again displayed a fast removal. However, the SAC VD BPSG film that shown a better removal rate than the PECVD PSG film is different with the deposited film characteristic. From a series of analysis by FT-IR instrument, the control wafer deposited with different sacrificial films above, then processed with the rapid thermal anneal or furnace anneal process showed that the boron (B) content decrease after thermal anneal was the dominator for the wet etch property performed.

The formation condition, microstructure, and growth kinetics of the WO x layer for WO x resistive random access memory are investigated. To understand the optimal condition for the rapid thermal oxidation process which forms the WO x layer, various annealing temperature and annealing time are systemically studied through transmission electron microscopy, X-ray diffraction, Raman spectra analyses and electrical characterizations. The growth kinetics for WO x under rapid thermal oxidation is found similar to the one for thermal oxidation on silicon. The electrical forming voltages of the WO x cells are also found independent from the oxide thickness, which further suggests the switching behavior of WO x resistive random access memory takes place at the interface but not the bulk.