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The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods. [ABSTRACT FROM AUTHOR]