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We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and $2 \times 2$ ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient $6 \times 6$ approximate ternary multipliers. The energy benefit of the proposed $6 \times 6$ approximate ternary multipliers have been verified using HSPICE simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user’s requirement.

This paper presents a convolutional neural network (CNN) accelerator that can skip zero weights and handle outliers, which are few but have a significant impact on the accuracy of CNNs, to achieve speedup and increase the energy efficiency of CNN. We propose an offline weight-scheduling algorithm which can skip zero weights and combine two non-outlier weights simultaneously using bit-level sparsity of CNNs. We use a reconfigurable multiplier-and-accumulator (MAC) unit for two purposes; usually used to compute combined two non-outliers and sometimes to compute outliers. We further improve the speedup of our accelerator by clipping some of the outliers with negligible accuracy loss. Compared to DaDianNao [7] and Bit-Tactical [16] architectures, our CNN accelerator can improve the speed by 3.34 and 2.31 times higher and reduce energy consumption by 29.3% and 30.2%, respectively.

Convolutional neural networks (CNNs) require a huge amount of off-chip DRAM access, which accounts for most of its energy consumption. Compression of feature maps can reduce the energy consumption of DRAM access. However, previous compression methods show poor compression ratio if the feature maps are either extremely sparse or dense. To improve the compression ratio efficiently, we have exploited the spatial correlation and the distribution of non-zero activations in output feature maps. In this work, we propose a grid-based run-length compression (GRLC) and have implemented a hardware for the GRLC. Compared with a previous compression method [1], GRLC reduces 11% of the DRAM access and 5% of the energy consumption on average in VGG-16, ExtractionNet and ResNet-18.

Owing to the growth of the size of convolutional neural networks (CNNs), quantization and loop tiling (also called loop breaking) are mandatory to implement CNN on an embedded system. However, channel loop tiling of quantized CNNs induces unexpected errors. We explain why channel loop tiling of quantized CNNs induces the unexpected errors, and how the errors affect the accuracy of state-of-the-art CNNs. We also propose a method to recover accuracy under channel tiling by compressing and decompressing the most-significant bits of partial sums. Using the proposed method, we can recover accuracy by 12.3% with only 1% circuit area overhead and an additional 2% of power consumption.

Convolutional neural networks (CNNs) are computationally intensive, and deep learning hardware should be implemented energy-efficiently for embedded systems or battery-constrained systems. In this paper, we propose an outlier-aware time-multiplexing MAC. We exploit a CNN feature maps' characteristic of being able to express most of the data in a low bit-width except a few large values, which we call ‘outliers' Our outlier-aware time-multiplexing MAC has improved the energy efficiency by up to 21.1% compared to conventional MACs.

Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM . Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12&times, read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

The portability of emerging computing systems demands further reduction in the power consumption of their components. Approximate computing can reduce power consumption by using a simplified or an inaccurate circuit. In this paper, the energy efficiency of a finite impulse response (FIR) filter is improved through approximate computing. We propose an approximate synthesis technique for an energy-efficient FIR filter with an acceptable level of accuracy. We employ the common subexpression elimination (CSE) algorithm to implement the FIR filter and replace conventional adder/subtractors with approximate ones. While yielding acceptable rates of accuracy, the proposed flow can attain a maximum energy saving of 50.7% in comparison with conventional FIR filter designs.

As the technology node has scaled down below 32 nm, the supply voltage has decreased to 1V and the current demands for active devices have increased. Therefore, the supply noise due to the IR drop in the power delivery network (PDN) has become a critical problem for robust circuit operation. Huge decoupling capacitors are introduced to overcome the supply voltage fluctuations. In this study, we investigate a 32-nm double-gate FinFET device for a decoupling capacitor in the PDN. The circuit designers can independently control both the gates in the double-gate FinFET. We compare the supply and ground noise reduction in the conventional planar CMOS and in various FinFET structures in a PEEC-based practical PDN and propose the best decoupling capacitor design strategy for double-gate FinFETs. The simulation results show that we can achieve an increased reduction in the supply voltage noise up to 50% by shorting the front gate and back gate together.

This paper presents a simple and accurate model for determining I on and I off of a double-gate FinFET with varying gate fin shapes. Simulations show that gate fin shape variation results in significant changes in the leakage and driving capability of the device. We perform TCAD simulations of double-gate FinFET structures in order to analyze the effect of the gate fin body thickness (T si ) variation on the electrical properties of the device. The thicknesses of the source and drain side are found to have different effects on the device. A simple model is proposed using the threshold voltage change due to the thickness variation along the gate fin. Simulation results show that the models match well with I on and I off within 1.3% and 4.8% errors, respectively. In addition, we propose an optimal fin body shape to reduce the leakage current while providing a similar driving current to that in the nominal FinFET.