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This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply.

Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area.

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area.

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area.

In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply.

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature independent voltage reference suitable for low voltage and ultra-low power bio-medical applications. The technique presented here uses only MOS transistors to generate PTAT and CTAT currents. A selfbiasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm, and at room temperature it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from -40 to 1250C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/0C.