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Abstract Compute-in-memory based on resistive random-access memory has emerged as a promising technology for accelerating neural networks on edge devices. It can reduce frequent data transfers and improve energy efficiency. However, the nonvolatile nature of resistive memory raises concerns that stored weights can be easily extracted during computation. To address this challenge, we propose RePACK, a threefold data protection scheme that safeguards neural network input, weight, and structural information. It utilizes a bipartite-sort coding scheme to store data with a fully on-chip physical unclonable function. Experimental results demonstrate the effectiveness of increasing enumeration complexity to 5.77 × 1075 for a 128-column compute-in-memory core. We further implement and evaluate a RePACK computing system on a 40 nm resistive memory compute-in-memory chip. This work represents a step towards developing safe, robust, and efficient edge neural network accelerators. It potentially serves as the hardware infrastructure for edge devices in federated learning or other systems.

Abstract Wireless internet-of-things (WIoT) with data acquisition sensors are evolving rapidly and the demand for transmission efficiency is growing rapidly. Frequency converter that synthesizes signals at different frequencies and mixes them with sensor datastreams is a key component for efficient wireless transmission. However, existing frequency converters employ separate synthesize and mix circuits with complex digital and analog circuits using complementary metal-oxide semiconductor (CMOS) devices, naturally incurring excessive latency and energy consumption. Here we report a highly uniform and calibratable VO2 memristor oscillator, based on which we build memristor-based frequency converter using 8 $$\times$$ × 8 VO2 array that can realize in-situ frequency synthesize and mix with help of compact periphery circuits. We investigate the self-oscillation based on negative differential resistance of VO2 memristors and the programmability with different driving currents and calibration resistances, demonstrating capabilities of such frequency converter for in-situ frequency synthesize and mix for 2 ~ 8 channels with frequencies up to 48 kHz for low frequency transmission link. When transmitting classical sensor data (acoustic, vision and spatial) in an end-to-end WIoT experimental setup, our VO2-based memristive frequency converter presents up to 1.45× ~ 1.94× power enhancement with only 0.02 ~ 0.21 dB performance degradations compared with conventional CMOS-based frequency converter. This work highlights the potential in solving frequency converter’s speed and energy efficiency problems in WIoT using high crystalline quality epitaxially grown VO2 and calibratable VO2-based oscillator array, revealing a promising direction for next-generation WIoT system design.

Epilepsy is a prevalent neurological disorder, rendering the development of automated seizure detection systems imperative. While complex machine learning models are powerful, their training and hardware deployment remain challenging. The reservoir computing system offers a low-cost solution in terms of both hardware requirements and training. In this paper, we introduce a compact reservoir computing system for seizure detection, based on the α-In2Se3 dynamic memristors. Leaky integrate-and-fire neurons are used for post-processing the output of the system, and experimental results indicate their effectiveness in suppressing erroneous outputs, where both accuracy and specificity are enhanced by over 2.5%. The optimized compact reservoir system achieves 96.40% accuracy, 86.34% sensitivity, and 96.56% specificity in seizure detection tasks. This work demonstrates the feasibility of using reservoir computing for seizure detection and shows its potential for future application in extreme edge devices.

Abstract Humans are complex organisms made by millions of physiological systems. Therefore, physiological activities can represent physical or mental states of the human body. Physiological signal processing is essential in monitoring human physiological features. For example, non‐invasive electroencephalography (EEG) signals can be used to reconstruct brain consciousness and detect eye movements for identity verification. However, physiological signal processing requires high resolution, high sensitivity, fast responses, and low power consumption, hindering practical hardware design for physiological signal processing. The bionic capability of memristor devices is very promising in the context of building physiological signal processing hardware and they have demonstrated a handful of advantages over the traditional Von Neumann architecture system in accelerating neural networks. Memristor networks can be integrated as a hardware system for physiological signal processing that can deliver higher energy efficiency and lower latency compared to traditional implementations. This review paper first introduces memristor characteristics, followed by a comprehensive literature study of memristor‐based networks. Physiology signal processing applications enabled by these integrated memristor networks are also presented in this review. In summary, this paper aims to provide a new perspective on physiological signal processing using integrated memristor networks.

Deep neural networks (DNNs) are one of the key fields of machine learning. It requires considerable computational resources for cognitive tasks. As a novel technology to perform computing inside/near memory units, in-memory computing (IMC) significantly improves computing efficiency by reducing the need for repetitive data transfer between the processing and memory units. However, prior IMC designs mainly focus on the acceleration for DNN inference. DNN training with the IMC hardware has rarely been proposed. The challenges lie in the requirement of DNN training for high precision (e.g. floating point (FP)) and various operations of tensors (e.g. inner and outer products). These challenges call for the IMC design with new features. This paper proposes a novel Hadamard product-based IMC design for FP DNN training. Our design consists of multiple compartments, which are the basic units for the matrix element-wise processing. We also develop BFloat16 post-processing circuits and fused adder trees, laying the foundation for IMC FP processing. Based on the proposed circuit scheme, we reformulate the back-propagation training algorithm for the convenience and efficiency of the IMC execution. The proposed design is implemented with commercial 28 nm technology process design kits and benchmarked with widely used neural networks. We model the influence of the circuit structural design parameters and provide an analysis framework for design space exploration. Our simulation validates that MobileNet training with the proposed IMC scheme saves $91.2\%$ in energy and $13.9\%$ in time versus the same task with NVIDIA GTX 3060 GPU. The proposed IMC design has a data density of 769.2 Kb mm ^−2 with the FP processing circuits included, showing a 3.5 × improvement than the prior FP IMC designs.